USBN9603-28M/NOPB National Semiconductor, USBN9603-28M/NOPB Datasheet - Page 38

• Manufacturer Part Number: USBN9603-28M/NOPB
• Description: IC CONTROLLER USB 28-SOIC
• Manufacturer: National Semiconductor

Specifications of USBN9603-28M/NOPB

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Usb Type: Node Controller
• Usb Version: 1.1
• No. Of Ports: 2
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Rohs Compliant: Yes
• For Use With: USBN9604-HS-EB - KIT NODE CONTROLLER SAMPLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *USBN9603-28M; *USBN9603-28M/NOPB; USBN9603-28M

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7.0 Register Set
7.2.5
This register sets the device function address. The different endpoint numbers are set for each endpoint individually via the
Endpoint Control registers.
AD
Address. This field holds the 7-bit function address used to transmit and receive all tokens addressed to the device.
AD_EN
Address Enable. When set to 1, bits AD6-0 are used in address comparison (see Section 6.2 for a description). When
cleared, the device does not respond to any token on the USB bus.
Note: If the DEF bit in the Endpoint Control 0 register is set, Endpoint 0 responds to the default address.
7.2.6
DSRC
DMA Source. The DMA source bit field holds the binary-encoded value that specifies which of the endpoints, 1 to 6, is en-
abled for DMA support. The DSRC bits are cleared on reset. Table 7 summarizes the DSRC bit settings.
DMOD
DMA Mode. This bit specifies when a DMA request is issued. If reset, a DMA request is issued on transfer completion. For
transmit endpoints EP1, EP3 and EP5, the data is completely transferred as indicated by the TX_DONE bit (to fill the FIFO
with new transmit data). For receive endpoints EP2, EP4 and EP6, this is indicated by the RX_LAST bit. When the DMOD
bit is set, a DMA request is issued when the respective FIFO warning bit is set. The DMOD bit is cleared on reset.
Function Address Register (FAR)
DMA Control Register (DMACNTRL)
DEN
bit 7
r/w
AD_EN
0
bit 7
r/w
0
(Continued)
IGNRXTGL
bit 6
r/w
0
bit 6
0
DTGL
bit 5
2
0
0
0
0
1
1
1
r/w
0
bit 5
Table 7. DSRC Bit Description
0
DSRC
1
0
0
1
1
0
0
1
ADMA
bit 4
r/w
bit 4
0
0
0
0
1
0
1
0
1
x
38
DMOD
AD6-0
bit 3
bit 3
r/w
r/w
0
Endpoint No.
0
Reserved
1
2
3
4
5
6
bit 2
bit 2
0
0
DSRC2-0
bit 1
bit 1
r/w
0
bit 0
bit 0
0
0