CP2200-GQ Silicon Laboratories Inc, CP2200-GQ Datasheet - Page 78
![IC ETH CTRLR SNGL-CHIP 48TQFP](/photos/6/82/68266/cp2200-gq_sml.jpg)
CP2200-GQ
Manufacturer Part Number
CP2200-GQ
Description
IC ETH CTRLR SNGL-CHIP 48TQFP
Manufacturer
Silicon Laboratories Inc
Specifications of CP2200-GQ
Package / Case
48-TQFP, 48-VQFP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
Parallel/Serial
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
75mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Ethernet Connection Type
1000BASE-T or 100BASE-T or 10BASE-T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps or 100 Mbps or 1000 Mbps
Maximum Operating Temperature
+ 85 C
No. Of Ports
1
Ethernet Type
IEEE 802.3
Interface Type
Parallel
Supply Current
60mA
Supply Voltage Range
3.1V To 3.6V
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1312
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CP2200/1
14. Media Access Controller (MAC)
The CP2200/1 has an IEEE 802.3 compliant Ethernet Media Access Controller (MAC). The MAC can be
configured to automatically pad short frames (full duplex mode only), append CRC, and perform frame length
checking. A loopback mode separate from PHY loopback is also provided for system debugging. The MAC is
configured through nine indirect 16-bit registers summarized in Table 20.
14.1. Initializing the MAC
MAC initialization occurs after the physical layer initialization and typically occurs once after each reset or Auto-
Negotiation Complete interrupt. Most MAC indirect registers can be left at their reset values. See “6.2. Reset
Initialization” on page 18 for the complete reset initialization procedure. The following are the steps required to
initialize the MAC:
14.2. Accessing the Indirect MAC Registers
The indirect MAC registers are accessed through four direct mapped registers: MACADDR, MACDATAH,
MACDATAL, and MACRW. The MAC registers can be accessed using the following procedure:
78
Step 1: Determine if the physical layer is set to full-duplex or half-duplex. The MAC must be set to the same
Step 2: Write 0x40B3 (full-duplex) or 0x4012 (half-duplex) to MACCF. The appropriate bits in this register
Step 3: Write 0x0015 (full-duplex) or 0x0012 (half-duplex) to IPGT.
Step 4: Write 0x0C12 to IPGR.
Step 5: Write 0x05EE to MAXLEN.
Step 6: Program the 48-bit Ethernet MAC Address by writing to MACAD0:MACAD1:MACAD2.
Step 7: Write 0x0001 to MACCN to enable reception. If loopback mode or flow control is desired, set the
Step 1: Write the address of the indirect register to MACADDR.
Step 2: If writing a value to the indirect register, write a 16-bit value to MACDATAH:MACDATAL.
Step 3: Write any value to MACRW to transfer the contents of MACDATAH:MACDATAL to the indirect
Step 4: Perform a read on MACRW to transfer the contents of the indirect register to
duplex mode as the physical layer before sending or receiving any packets.
may also be set or cleared to change padding options or MAC behavior.
appropriate bits to enable these functions.
register.
MACDATAH:MACDATAL. The MACDATAH and MACDATAL registers may now be directly read to
determine the contents of the indirect register.
Rev. 1.0