CP2200-GQ Silicon Laboratories Inc, CP2200-GQ Datasheet
CP2200-GQ
Specifications of CP2200-GQ
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CP2200-GQ Summary of contents
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... Network clocks Embedded Web Server Remote Ethernet-to-UART bridge Supply Voltage 3.1 to 3.6 V Package Pb-free 48-pin TQFP (9x9 mm footprint) Pb-free 28-pin QFN (5x5 mm footprint) Ordering Part Number CP2200-GQ (48-pin) CP2201-GM (28-pin) Temperature Range: –40 to +85 °C 20 MHz XTAL LED 8 kB Clock Control ...
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... CP2200/1 2 Rev. 1.0 ...
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... Transmit Buffer and AutoWrite Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.5. Transmit Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12. Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.2. Reading a Packet Using the Autoread Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3. Timing and Buffer Overflow Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.4. Initializing the Receive Buffer, Filter and Hash Table . . . . . . . . . . . . . . . . . . . . . . . 59 Rev. 1.0 CP2200/1 Page 3 ...
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... CP2200/1 12.5. Receive Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.6. Advanced Receive Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.7. Receive Buffer Advanced Status and Control Registers . . . . . . . . . . . . . . . . . . . . .67 13. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.1. Programming the Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.2. Reading the Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.3. Flash Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14. Media Access Controller (MAC ...
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... Controller (MAC), 10BASE-T Physical Layer (PHY), and 8 kB Non-Volatile Flash Memory available in a compact QFN-28 package (sometimes called “MLF” or “MLP”) and a 48-pin TQFP package. The CP2200/1 can add Ethernet connectivity to any microcontroller or host processor with 11 or more Port I/O pins. The 8-bit parallel interface bus supports both Intel and Motorola bus formats in multiplexed and non-multiplexed mode ...
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... CP2200/1 2. Typical Connection Diagram Figure 2 and Figure 3 show typical connection diagrams for the 48-pin CP2200 and 28-pin CP2201. 0.1 uF 0.1 uF XTAL1 10 MΩ 20 MHz XTAL2 MCU Optional A15 CS 8 A[7:0] A[7:0] 8 D[7:0] D[7: Optional INT INT DGND1 DGND2 GND AGND Note: The CP220x should be placed within 1 inch of the transformer for optimal performance. ...
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... Note: The CP220x should be placed within 1 inch of the transformer for optimal performance. Figure 3. Typical Connection Diagram (Multiplexed) +3VD 0 RST MOTEN LA CP2201 8 Ω TX+ 0.001 uF 0.001 uF TX– 8 Ω 0.1 uF RX+ RX– 0.1 uF Rev. 1.0 CP2200/1 +3VD 4.7 kΩ LINK/ACTIVITY Integrated RJ-45 Jack 1:2.5 TXP RJ-45 1 TXN 2 3 TCT 1:1 RXP 7 100 Ω ...
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... CP2200/1 3. Absolute Maximum Ratings Table 1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current through V DD Maximum output current sunk by RST or any I/O pin Note: Stresses above those listed may cause permanent damage to the device ...
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... Conditions Min I = – – 0 –10 µA V – 0 –10 mA — 8.5 mA — µA — — OL 2.0 — — Rev. 1.0 CP2200/1 Typ Max Units 3.3 3 155 mA 60 — — — mA 6.5 — mA — +85 °C Typ Max UNITS — — V — — V – 0.8 — ...
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... INT 42 25 *Note: Pins can be left unconnected when not used. 10 Table 4. CP2200/1 Pin Definitions Type Analog Ground Digital Ground Digital Ground D I/O Device Reset. Open-drain output of internal POR and V An external source can initiate a system reset by driving this pin low for at least 15 µ ...
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... Table 4. CP2200/1 Pin Definitions (Continued) Name Pin Numbers 48-pin 28-pin RD/(DS WR/(R/ D0/AD0 16 11 D1/AD1 17 12 D2/AD2 18 13 D3/AD3 19 14 D4/AD4 20 15 D5/AD5 21 16 D6/AD6 22 17 D7/AD7 27* — A1 28* — A2 29* — A3/ALE/(AS) 32 — ALE/(AS) — 33* — A5 34* — A6 37* — ...
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... CP2200 ACT 2 LINK 3 AGND 4 AV+ 5 RX TX Figure 4. 48-pin TQFP Pinout Diagram 12 CP2200 Top View Rev. 1 A3/ALE/(AS DGND2 VDD2 ...
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... PIN 1 IDENTIFIER Figure 5. 48-pin TQFP Package Dimensions Table 5. TQFP-48 Package Rev. 1.0 CP2200/1 Dimensions MM Min Typ Max — — 1.20 0.05 — 0.15 0.95 1.00 1.05 0.17 0.22 0.27 — 9.00 — — 7.00 — — 9.00 — — 0.50 — ...
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... CP2200/1 GND LA 1 AGND 2 AV+ 3 RX- 4 RX+ 5 TX+ 6 TX- 7 Figure 6. QFN-28 Pinout Diagram (Top View) 14 CP2201 Top View GND Rev. 1.0 21 ALE/(AS) 20 DGND2 19 VDD2 18 AD7 17 AD6 16 AD5 15 AD4 ...
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... D2 2.90 E — 2. — L 0.45 N — ND — NE — R 0.09 AA — BB — CC — DD — Rev. 1.0 CP2200/1 MM Typ Max 0.90 1.00 0.02 0.05 0.65 1.00 0.25 — 0.23 0.30 5.00 — 3.15 3.35 5.00 — 3.15 3.35 0.5 — 0.55 0.65 28 — 7 — ...
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... CP2200/1 0.50 mm 0.20 mm Optional GND Connection L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 8. Typical QFN-28 Landing Diagram 16 Top View E2 E Rev. 1.0 0.85 mm ...
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... L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 9. Typical QFN-28 Solder Paste Diagram Top View 0.60 mm 0.30 mm 0. Rev. 1.0 CP2200/1 0. ...
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... Step 9: The CP2200/1 is ready to transmit and receive packets. 6.3. Interrupt Request Signal The CP2200/1 has an interrupt request signal (INT) that can be used to notify the host processor of pending interrupts. The INT signal is asserted upon detection of any enabled interrupt event. Host processors that cannot dedicate a port pin to the INT signal can periodically poll the interrupt status registers to see if any interrupt generating events have occurred ...
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... MHz CMOS Clock Figure 11. External CMOS Clock Example Table 7 lists the clocking requirements of the CP2200/1 when using a crystal oscillator or CMOS clock. Table 8 shows the electrical characteristics of the XTAL1 pin. These characteristics are useful when selecting an external CMOS clock. XTAL1 20 MHz 10 MΩ ...
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... CP2200/1 Table 7. Clocking Requirements V = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Frequency Frequency Error Duty Cycle Table 8. Input Clock Pin (XTAL1) DC Electrical Characteristics V = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters XTAL1 Input Low Voltage XTAL1 Input High Voltage ...
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... CP2200 ACT CP2200 LA CP2201 Figure 12 shows a typical LED connection for the CP2200. The CP2201 uses an identical connection for the LA (link/activity) pin. The LED drivers are enabled and disabled using the IOPWR register on page 45. LINK ACT Figure 12. LED Control Example (CP2200) Table 9. ...
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... CP2200/1 6.6. Sending and Receiving Packets After reset initialization is complete, the CP2200/1 is ready to send and receive packets. Packets are sent by loading data into the transmit buffer using the AutoWrite register and writing ‘1’ to TXGO. See “11.2. Transmitting a Packet” on page 48 for detailed information on how to transmit a packet using the transmit interface. A Packet Transmitted interrupt will be generated once transmission is complete ...
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... Internal Memory and Registers The CP2200/1 is controlled through direct and indirect registers accessible through the parallel host interface. The host interface provides an 8-bit address space, of which there are 114 valid direct register locations (see Table 11 on page 25). All remaining addresses in the memory space are reserved and should not be read or written. The direct registers provide access to the RAM buffers, Flash memory, indirect MAC configuration registers, and other status and control registers for various device functions ...
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... CP2200/1 Register 1. RAMADDRH: RAM Address Pointer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: RAMADDRH: RAM Address Register High Byte Holds the most significant eight bits of the target RAM address. Register 2. RAMADDRL: RAM Address Pointer Low Byte R/W R/W ...
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... Internal Registers The CP2200/1 has 114 direct internal registers and 9 indirect registers. The registers are grouped into ten categories based on function. Table 10 lists the register groups and provides links to the detailed register descriptions for each group. Table 11 lists all direct registers available on the device. ...
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... CP2200/1 Register Address INT0 0x63 INT0EN 0x64 INT0RD 0x76 INT1 0x7F INT1EN 0x7D INT1RD 0x7E IOPWR 0x70 MACADDR 0x0A MACDATAH 0x0B MACDATAL 0x0C MACRW 0x0D OSCPWR 0x7C PHYCF 0x79 PHYCN 0x78 PHYSTA 0x80 RAMADDRH 0x08 RAMADDRL 0x09 RAMRXDATA 0x02 RAMTXDATA 0x04 ...
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... TLB2 Length Low Byte TLB3 Address High Byte TLB3 Address Low Byte TLB3 Information High Byte TLB3 Information Low Byte TLB3 Length High Byte TLB3 Length Low Byte TLB4 Address High Byte Rev. 1.0 CP2200/1 Page No. page 62 page 63 page 61 page 40 page 70 page 70 page 68 ...
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... CP2200/1 Register Address TLB4ADDRL 0x40 TLB4INFOH 0x3B TLB4INFOL 0x3C TLB4LENH 0x3D TLB4LENL 0x3E TLB5ADDRH 0x45 TLB5ADDRL 0x46 TLB5INFOH 0x41 TLB5INFOL 0x42 TLB5LENH 0x43 TLB5LENL 0x44 TLB6ADDRH 0x4B TLB6ADDRL 0x4C TLB6INFOH 0x47 TLB6INFOL 0x48 TLB6LENH 0x49 TLB6LENL 0x4A TLB7ADDRH 0x51 TLB7ADDRL 0x52 ...
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... Transmit Status Vector 2 Transmit Status Vector 3 Transmit Status Vector 4 Transmit Status Vector 5 Transmit Status Vector 6 Transmit Data Starting Address High Byte Transmit Data Starting Address Low Byte V Monitor Control Register DD Rev. 1.0 CP2200/1 Page No. page 52 page 52 page 46 page 57 page 56 page 56 page 55 page 55 page 54 ...
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... CP2200/1 8. Interrupt Sources The CP2200/1 can alert the host processor when any of the 14 interrupt source events listed in Table 12 triggers an interrupt. The CP2200/1 alerts the host by setting the appropriate flags in the interrupt status registers and driving the INT pin low. The INT pin will remain asserted until all interrupt flags for enabled interrupts have been cleared by the host ...
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... RXINT: Packet Received Interrupt Flag 0: A packet has not been added to the receive buffer since the last time RXINT was cleared packet has been added to the receive buffer TXINT RXFINT Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 RC Reset Value RXINT 00000000 Bit0 Address: 0x63 31 ...
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... CP2200/1 Register 6. INT0RD: Interrupt Status Register 0 (Read-Only EOPINTR RXEINTR SELFINTR OSCINTR FLWEINTR TXINTR RXFINTR RXINTR 00000000 Bit7 Bit6 Bit5 Note: Reading this register will not clear INT0 interrupt flags. Bit 7: EOPINTR: End of Packet Read-Only Interrupt Flag 0: The last byte of a packet has not been read since the last time EOPIF was cleared. ...
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... Disable Receive FIFO Full Interrupt. 1: Enable Receive FIFO Full Interrupt. Bit 0: ERXINT: Enable Packet Received Interrupt 0: Disable Packet Received Interrupt. 1: Enable Packet Received Interrupt. R/W R/W R/W R/W ERXFINT ERXINT 00000000 Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Reset Value Bit0 Address: 0x64 33 ...
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... CP2200/1 Register 8. INT1: Interrupt Status Register 1 (Self-Clearing) R/W R/W RC — — WAKEINT LINKINT Bit7 Bit6 Bit5 Note: Reading this register will clear all INT1 interrupt flags. Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: WAKEINT: “Wake-on-Lan” Interrupt Flag 0: The device has not been connected to a network since the last time WAKEINT was cleared ...
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... Auto-Negotiation has not failed since the last time ANFINT was cleared. 1: Auto-Negotiation has failed. Bit 1: Reserved: Read = 0b. Bit 0: ANCINTR: Auto-Negotiation Complete Read-Only Interrupt Flag 0: Auto-Negotiation has not completed since the last time ANCINT was cleared. 1: Auto-Negotiation has completed Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R Reset Value Bit0 Address: 0x7E 35 ...
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... CP2200/1 Register 10. INT1EN: Interrupt Enable Register 1 R/W R/W R/W — — EWAKEINT ELINKINT EJABINT EANFINT Reserved EANCINT 00000000 Bit7 Bit6 Bit5 Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: EWAKEINT: Enable “Wake-on-Lan” Interrupt 0: Disable “Wake-on-Lan” Interrupt. 1: Enable “Wake-on-Lan” Interrupt. ...
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... The CP2200/1 has five reset sources that place the device in the reset state. The method of entry to the reset state determines the amount of time spent in reset and the behavior of the /RST pin. Each of the following reset sources ...
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... CP2200/1 9.1. Power-On Reset During power-up, the CP2200/1 is held in the reset state, and the /RST pin is driven low until delay (T ) occurs between the time V RST PORDelay reset; the typical delay is 5 ms. Refer to Table 13 for the Electrical Characteristics of the power supply monitor circuit ...
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... If the system clock derived from the oscillator fails for any reason after oscillator initialization is complete, the reset circuitry will drive the /RST pin low and return the CP2200/1 to the reset state. The CP2200/1 will remain in the reset state for approximately 1 ms then exit the reset state in the same manner as that for the power-on reset. ...
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... CP2200/1 9.5. Software Reset The software reset provides the host CPU the ability to reset the CP2200/1 through the parallel host interface. Writing a ‘1’ to RESET (SWRST.2) will force the device to enter the reset state with the exception that the external oscillator will not be stopped. As soon as the device enters the reset state, it will immediately exit the reset state and start device calibration ...
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... Source of last reset was a power-on, power-fail, or oscillator-fail event. Bit 0: PINRSI: External Pin Reset Indicator 0: Source of last reset was not the /RST pin. 1: Source of last reset was the /RST pin. R/W R — — SWRSI PORSI Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R Reset Value PINRSI 00000000 Bit0 Address: 0x73 41 ...
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... CP2200/1 9.7. De-Selecting Interrupt Sources The power-fail (V Monitor) reset is automatically enabled after every power-on reset. The software reset is DD enabled after every device reset, regardless of the reset source. The RSTEN register can be used to prevent either of these two reset sources from generating a device reset. ...
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... Power Modes The CP2200/1 has four power modes that can be used to minimize overall system power consumption. The power modes vary in device functionality and recovery methods. Each of the following power modes is explained in the following sections: Normal Mode (Device Fully Functional) Link Detection Mode (Transmitter Disabled) ...
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... CP2200/1 10.1. Normal Mode Normal Mode should is used whenever the host is sending or receiving packets. In this mode, the CP2200/01 is fully functional. Typical Normal Mode power consumption is listed in Table 2 on page 9. Note: When in normal mode, the transmitter has a power saving mode which is enabled on reset. This power saving mode dis- ables the transmitter's output driver and placed the TX+/- pins in high impedance when the CP220x is not transmitting link pulses or data ...
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... Weak pull-ups are enabled. 1: Weak pull-ups are disabled. Bit 0: Reserved. Read = 0b; Must write 0b. Monitor can be disabled to minimize power consumption. The typical DD R/W R/W R/W R/W — ACTEN LINKEN WEAKD Reserved 00000000 Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Reset Value Bit0 Address: 0x70 45 ...
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... CP2200/1 Register 16. OSCPWR: Oscillator Power Register R/W R/W R/W — — — Bit7 Bit6 Bit5 Bits 7–5: UNUSED. Read = 0000b, Write = don’t care. Bit 4–2: RESERVED. Read = 100b; Must write x00b. Bit 1: UNUSED. Read = 1b; Write = don’t care. Bit 0: OSCOE: Oscillator Output Enable This bit controls the output of the external oscillator ...
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... Transmit Interface 11.1. Overview The CP2200/1 provides a simple interface for transmitting Ethernet packets requiring the host to only load the source and destination addresses, length/type, and data into the transmit buffer. All other IEEE 802.3 requirements, such as the preamble, start frame delimiter, CRC, and padding (full-duplex only), are automatically generated ...
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... CP2200/1 11.2. Transmitting a Packet Once reset initialization is complete (See ), the CP2200/1 is ready to transmit Ethernet packets. The following procedure can be used to transmit a packet: Step 1: Wait for the previous packet to complete (TXBUSY == 0x00). The worst case time to transmit a packet is 500 ms in half-duplex mode with exponential backoff. ...
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... Transmit Status and Control Registers The CP2200 transmit interface is controlled and managed through the registers in Table 14. After each packet is transmitted, information about the last transmitted packet can be obtained from the 52-bit transmit status vector accessible through the TXSTA0 — TXSTA6 registers. The transmit status vector is described in Table 15. ...
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... CP2200/1 Table 15. Transmit Status Vector Description Bit Field Name 51 Transmitted VLAN Frame 50 Back Pressure Applied 49 Transmitted PAUSE Frame 48 Transmitted Control Frame 47-32 Total Bytes Transmitted 31 Transmit Under-Run 30 Jumbo Packet Detected 29 Late Collision Detected 28 Excessive Collisions Detected 27 Excessive Delay Detected 26 Delay Detected ...
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... Packet Transmit is not in progress. 1: Packet Transmit is in progress. R/W R/W R/W Bit4 Bit3 Bit2 — — — — Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W W Reset Value TXGO 00000000 Bit1 Bit0 Address: 0x53 R Reset Value TXBUSY 00000000 Bit0 Address: 0x54 51 ...
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... CP2200/1 Register 20. TXPAUSEH: Transmit Pause High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TXPAUSEH: Transmit Pause High Byte High byte of the 16-bit pause value sent in a PAUSE control packet. The pause value is in units of 512 bit times (512 bit times = 51.2 µs). ...
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... Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Reset Value 00000000 Bit0 Address: 0x57 R/W Reset Value 00000000 Bit0 Address: 0x58 R/W Reset Value 00000000 Bit0 Address: 0x03 ...
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... CP2200/1 Register 27. TXSTA6: Transmit Status Vector 6 R/W R/W R/W — — — Bit7 Bit6 Bit5 Note: This register contains bits 51–48 of the Transmit Status Vector. Bits 7–4: UNUSED. Read = 0000b, Write = don’t care. Bit 3. TXVLAN: Transmitted VLAN Frame 0: Transmitted frame had length/type field of 0x8100. ...
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... Transmitted packet did not have a multicast destination address. 1: Transmit packet had a multicast destination address Bit4 Bit3 Bit2 Bit1 TXEXDE TXDE TXBCAST TXMCAST 00000000 Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R Reset Value 00000000 Bit0 Address: 0x5E R Reset Value Bit0 Address: 0x5F 55 ...
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... CP2200/1 Register 31. TXSTA2: Transmit Status Vector TXOK TXTYPE TXLCERR TXCRCER TXCOL3 Bit7 Bit6 Bit5 Note: This register contains bits 23–16 of the Transmit Status Vector. Bit 7: TXOK: Transmit Successful 0: Transmission was aborted. 1: Transmission was successful. Bit 6: TXLOOR: Type Field Detected 0: Last packet’s type/length field was used as a length. ...
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... Note: This register contains bits 15–8 of the Transmit Status Vector. Bits 7–0: TXSTA0: Transmit Byte Count Low Byte The least significant 8-bits of the number of bytes in the last transmitted frame. Does not include bytes transmitted due to collided attempts Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R Reset Value 00000000 Bit0 Address: 0x62 57 ...
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... Receive Interface 12.1. Overview The CP2200/1 has a 4k circular receive FIFO buffer and an 8 entry translation look-aside buffer (TLB) capable of storing packets at a time. Each TLB entry holds the starting address, length, and other information about a single received packet. Once a packet is received, the host microcontroller is notified using the interrupt request pin. The host microcontroller may then copy the contents of the packet to its local memory through the host interface or skip the packet by writing ‘ ...
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... If multicast packets need to be accepted, then the hash table can be programmed to accept packets addressed to specific address ranges. The CP2200/1 implements a 16-bit hash table to represent all possible addresses in the 64-bit address space. Each of the possible 65536 possible values for the hash table represent a range of MAC addresses. If all 16 bits are set to ‘ ...
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... CP2200/1 12.5. Receive Status and Control Registers The CP2200/1 receive interface is controlled and managed through the registers in Table 16. The current packet registers provide information about the next packet to be unloaded from the receive buffer (the oldest packet received). Table 16. Receive Status and Control Register Summary ...
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... Receive interface is currently receiving a packet. R/W R — RXINH RXCLRV RXSKIP RXCLEAR 00000000 Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R — — — CPEND Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 W Reset Value Bit0 Address: 0x11 R Reset Value RXBUSY 00000000 Bit0 Address: 0x12 61 ...
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... CP2200/1 Register 36. RXAUTORD: Receive AutoRead Data Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: RXAUTORD: Receive AutoRead Data Register Reads from this register read a single byte from the receive buffer and adjust the receive buffer pointer RXFIFOHEAD accordingly. Register 37. RXFILT: Receive Filter Configuration ...
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... Current packet is not a multicast packet. 1: Current packet is a multicast packet. R/W R/W R/W Bit4 Bit3 Bit2 RXPCF RXCF RXADATA BCAST Bit4 Bit3 Bit2 Rev. 1.0 CP2200/1 R/W R/W Reset Value 00000000 Bit1 Bit0 Address: 0x0F R R Reset Value MCAST 00000000 Bit1 Bit0 Address: 0x1D 63 ...
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... CP2200/1 Register 41. CPINFOL: Current Packet Information Low Byte RXOK LENGTH LENERR CRCERR Reserved Reserved Bit7 Bit6 Bit5 Bit 7: RXOK: Receive OK 0: Receive not OK. 1: Receive OK. Bit 6: LENGTH: Length/Type Field Detection 0: The length/type field of the current packet contains the packet length. 1: The length/type field of the current packet contains the packet type. ...
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... Bits 7–0: CPADDRL: Current Packet Address Low Byte Low byte of the current packet starting address in the receive FIFO buffer Bit4 Bit3 Bit2 Bit1 Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R Reset Value 00000000 Bit0 Address: 0x21 R Reset Value 00000000 Bit0 Address: 0x22 65 ...
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... CP2200/1 12.6. Advanced Receive Buffer Operation Receive buffer operation is automatically handled by hardware and does not require any assistance from the host processor. Note: The information in this section is provided for reference purposes only and will typically not be used except when debugging a problem and additional control over the receive buffer is required. ...
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... Points to the beginning of the current packet and is incremented with each Auto Read. 0x18 0x5B Indicates the cause of the Receive FIFO Buffer Full interrupt. R/W R/W R/W R/W — — CPTLB Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 Description R/W Reset Value 00000000 Bit0 Address: 0x1A 67 ...
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... CP2200/1 Register 47. TLBVALID: TLB Valid Indicator R/W R/W R/W VAL7 VAL6 VAL5 Bit7 Bit6 Bit5 Bits 7–0: TLBVALID: TLB Valid Indicator Displays the valid bits for the eight TLB slots in a single byte. Note: This register may be used to clear multiple valid bits simultaneously. For all writes, bits with a value of ‘ ...
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... TLB4LENH: 0x3D; TLB5LENH: 0x43; TLB6LENH: 0x49; TLB7LENH: 0x4F Bits 7–0: TLBnLENH: TLBn Packet Length High Byte High byte of the packet length for the packet associated with TLBn RXLEN Bit4 Bit3 Bit2 Bit1 Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R Reset Value RXDROP 00000000 Bit0 R Reset Value 00000000 Bit0 69 ...
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... CP2200/1 Register 51. TLBnLENL: TLBn Packet Length Low Byte Bit7 Bit6 Bit5 Address: TLB0LENH: 0x26; TLB1LENH: 0x2C; TLB2LENH: 0x32; TLB3LENH: 0x38; TLB4LENH: 0x3E; TLB5LENH: 0x44; TLB6LENH: 0x4A; TLB7LENH: 0x50 Bits 7–0: TLBnLENL: TLBn Packet Length Low Byte Low byte of the packet length for the packet associated with TLBn. ...
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... Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Reset Value 00000000 Bit0 Address: 0x17 R/W Reset Value 00000000 Bit0 Address: 0x18 R/W Reset Value 00000000 Bit0 Address: 0x15 ...
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... CP2200/1 Register 58. RXFIFOSTA: Receive FIFO Status Register R/W R/W R/W — — — Bit7 Bit6 Bit5 This register is set by hardware and is valid after an RX FIFO Full Interrupt is generated or if TLBVALID equals 0xFF. Bits 7–2: UNUSED. Read = 000000b, Write = don’t care. ...
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... After programming Flash, the CP2200/1 should be reset in order to protect the device from errant Flash operations. The key codes for unlocking the CP2200/1 are 0xA5 and 0xF1. These codes must be written in sequence to the FLASHKEY register prior to each Flash write or erase operation. Note: To ensure the integrity of Flash contents, the on-chip V Monitor should not be disabled while the Flash memory is unlocked ...
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... CP2200/1 13.2. Reading the Flash Memory Flash reads occur much faster than Flash write or erase operations and are completed within the minimum read strobe time specified by the parallel host interface. Flash is read using the FLASHADDRH:FLASHADDRL, FLASHDATA, and FLASHAUTORD registers. The FLASHAUTORD register provides an efficient method of accessing sequential data in Flash by automatically incrementing the Flash address pointer after each read ...
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... Flash Access Registers The CP2200 Flash is accessed through the registers in Table 17. See the register tables following Table 17 for detailed register descriptions Table 19. Flash Access Register Summary Register Long Name FLASHSTA Flash Status FLASHKEY Flash Lock and Key FLASHADDRH Flash Address Register High and ...
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... CP2200/1 Register 60. FLASHKEY: FLASH Lock and Key Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: FLKEY: Flash Lock and Key Register This register must be written to unlock the Flash for writing or erasing. To unlock the Flash, first write 0xA5 and then 0xF1 to this register. The V unlocked ...
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... Bit2 Bit1 Bit4 B Bit2 Bit1 R/W R/W R/W R/W — — — Reserved Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Reset Value 00000000 Bit0 Address: 0x06 R Reset Value 00000000 Bit0 Address: 0x05 R/W Reset Value FLEGO 00000000 Bit0 Address: 0x6A 77 ...
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... CP2200/1 14. Media Access Controller (MAC) The CP2200/1 has an IEEE 802.3 compliant Ethernet Media Access Controller (MAC). The MAC can be configured to automatically pad short frames (full duplex mode only), append CRC, and perform frame length checking. A loopback mode separate from PHY loopback is also provided for system debugging. The MAC is configured through nine indirect 16-bit registers summarized in Table 20 ...
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... Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Reset Value 00000000 Bit0 Address: 0x0A R/W Reset Value 00000000 Bit0 Address: 0x0B R/W Reset Value 00000000 Bit0 Address: 0x0C ...
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... CP2200/1 14.3. Indirect MAC Register Descriptions The MAC is configured through nine indirect 16-bit registers listed in Table 20. See the figures following Table 20 for detailed register descriptions. Table 20. Indirect MAC Register Summary Register Long Name MACCN MAC Control MACCF MAC Configuration IPGT Back-to-Back Interpacket Delay ...
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... The MAC allows received packets to reach the receive interface. R/W R/W R/W R/W Reserved Bit12 Bit11 Bit10 Bit9 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Bit8 R/W Default Value RCVEN 0x8000 Bit0 MACADDR: 0x00 81 ...
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... CP2200/1 Indirect Register 2. MACCF: MAC Configuration Register R/W R/W R/W Reserved ABORTD EBBPD Bit15 Bit14 Bit13 R/W R/W R/W PADMD1 PADMD0 PADEN Bit7 Bit6 Bit5 Bit 15: Reserved. Read = 0b; Must write 0b. Bit 14: ABORTD: Abort Disable Bit 0: MAC will abort when excessive delay is detected and update the transmit status vector. ...
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... CRC 1 1 Pad short frames to 60 bytes, append CRC 1 1 Pad short frames to 64 bytes, append CRC 1 1 Auto Detect Tagged VLAN Frames (IEEE802.1q) If untagged: Pad to 60 bytes, append CRC If tagged: Pad to 64 bytes, append CRC Rev. 1.0 CP2200/1 Action 83 ...
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... CP2200/1 Indirect Register 3. IPGT: Back-to-Back Inter-Packet Gap Register R/W R/W R/W Bit15 Bit14 Bit13 R/W R/W R/W Reserved Bit7 Bit6 Bit5 Bits 15–7:Reserved. Read = 000000000b; Must write 000000000b. Bits 6–0: IPGT: Back-to-Back Inter-Packet Gap Register Sets the minimum delay between the end of any transmitted packet and the start of a new packet. ...
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... Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit12 Bit11 Bit10 Bit9 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Bit8 R/W Default Value 0x370F Bit0 MACADDR: 0x04 R/W Bit8 R/W Default Value 0x0600 Bit0 MACADDR: 0x05 85 ...
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... CP2200/1 Indirect Register 7. MACAD0: MAC Address 0 R/W R/W R/W Bit15 Bit14 Bit13 R/W R/W R/W Bit7 Bit6 Bit5 Bits 15–8:OCTET6: MAC Address, 6th Octet This field holds the sixth (least significant) octet of the MAC address. Bits 7–0: OCTET5: MAC Address, 5th Octet This field holds the fifth octet of the MAC address ...
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... This field holds the first (most significant) octet of the MAC address. R/W R/W R/W R/W OCTET2 Bit12 Bit11 Bit10 Bit9 R/W R/W R/W R/W OCTET1 Bit4 Bit3 Bit2 Bit1 Rev. 1.0 CP2200/1 R/W Bit8 R/W Default Value 0x0000 Bit0 MACADDR: 0x12 87 ...
Page 88
... CP2200/1 15. Physical Layer (PHY) The CP2200/1 has an IEEE 802.3 compliant 10 BASE-T Ethernet physical layer transceiver that includes a receiver, transmitter, auto-negotiation, loopback, jabber, smart squelch, polarity correction, and link integrity functions. If enabled, the auto-negotiation function automatically negotiates the speed of the data link and the duplex mode ...
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... IEEE 802.3). The host processor will be notified via the Jabber Detected Interrupt if a jabber condition is automatically handled by the hardware. Enabling the jabber function is recommended to ensure that the embedded system using the CP2200/1 for Ethernet communication does not generate a jabber condition on the wire. ...
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... CP2200/1 15.7. Initializing the Physical Layer The physical layer should be configured to the desired mode prior to setting the enable bit PHYEN (PHYCN.7). The following procedure should be used to initialize the physical layer: Step 1: If auto-negotiation is used, implement the synchronization procedure in Section 15.2 on page 88. ...
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... Incorrect link polarity has not been detected. 1: Incorrect link polarity detected. Link polarity has been automatically reversed. Bit 0: LINKSTA: Link Status Indicator 0: Link is bad. 1: Link is good. R R/W R DPLXMD LBMD LPRFAULT POLREV Bit4 Bit3 Bit2 Rev. 1.0 CP2200 Reset Value LINKSTA 00000000 Bit1 Bit0 Address: 0x78 91 ...
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... Bit 3: Reserved. Read = 0b; Must write 0b. Bit 2: ADPAUSE: Advertise Pause Packet Capability 0: Indicates (during auto-negotiation) that the CP2200/01 does not have pause packet capability. 1: Indicates (during auto-negotiation) that the CP2200/01 does have pause packet capability. Bit 1: AUTOPOL: Automatic Polarity Correction Enable Bit 0: Automatic receiver polarity correction is disabled ...
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... Receiver Low Squelch Level Physical Layer Startup Time AKDAMF AKDCMF ABDLF ABDAKMF ABDABMF 00000000 Bit4 Bit3 Bit2 Conditions Min 2.2 — — — Rev. 1.0 CP2200 Reset Value Bit1 Bit0 Address: 0x80 Typ Max UNITS 2.5 2.8 V 585 — mV 330 — ...
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... CP2200/1 Table 23. 10BASE-T Transmit Switching Characteristics V = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Symbol TX Pair Jitter into 100 Ω Load T TXJIT T TX Pair Positive Hold time at End of Packet TXHLD T TX Pair Return to < after Last Positive TXRET Transition Table 24. 10BASE-T Receive Switching Characteristics V = 3.1 to 3.6 V, – ...
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... Width of Transmitted Link Pulses TXLPW T Received Link Pulse Separation RXLP1 T Last Receive Activity to Link Fail LPLED T TXLP1 ... T TXLPW T LPLED ... Figure 21. 10BASE-T Link Integrity Description Min — — — Rev. 1.0 CP2200/1 T TXLP2 ... ... T RXLP1 ... ... Typ Max UNITS 16 — — ms 100 210 ns — 150 — ...
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... CP2200/1 16. Parallel Interface The CP2200/1 has an 8-bit parallel host interface used to access the direct registers on the device. The parallel interface supports multiplexed or non-multiplexed operation using the Intel pin can be driven high to place the device in multiplexed operation or driven low to select non-multiplexed operation. The MOTEN pin can be driven high to place the device in Motorola bus format or driven low to place the device in Intel bus format ...
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... Address Hold Time (Read) AHR T Address Hold Time (Write) AHW T Hold Delay (Read/Write) HOLD Min Typ 30 — 160 — — — — 60 120 — 40 — 20 — 30 — 30 — 60 — Rev. 1.0 CP2200/1 Max UNITS — ns — ns 140 ns — ns — ns — ns — ns — ns — ns — ...
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... CP2200/1 16.2. Multiplexed Intel Format ALE AD[7:0] RD Notes must be asserted with or before RD must remain de-asserted during a READ. ALE AD[7:0] WR Notes must be asserted with or before must remain de-asserted during a WRITE ALE1 ALE2 VD1 Valid Address T RD Figure 24. Multiplexed Intel READ T T ALE1 ...
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... DS T Data Hold Time (Write Hold Delay (Read/Write) HOLD Min Typ 40 — 40 — 40 — 40 — 160 — — — — 60 120 — 40 — 40 — 60 — Rev. 1.0 CP2200/1 Max UNITS — ns — ns — ns — ns — ns 140 ns — ns — ns — ns — ns — ...
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... CP2200/1 16.3. Non-Multiplexed Motorola Format A[7:0] /DS D[7:0] R/W Note: /CS must be asserted with or before /DS. Figure 26. Nonmuxed Motorola READ A[7:0] /DS D[7:0] R/W Note: /CS must be asserted with or before /DS. Figure 27. Nonmuxed Motorola WRITE 100 Valid Address T AHR HOLD DSR T T VD1 VD2 Valid Data T T RWS ...
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... R/W Hold Time (Read/Write) RWH T Hold Delay (Read/Write) HOLD Min Typ 30 — 30 — 160 — — — — 60 120 — 40 — 20 — 30 — 30 — 20 — 60 — Rev. 1.0 CP2200/1 Max UNITS — ns — ns — ns 140 ns — ns — ns — ns — ns — ns — ns — ns — ns 101 ...
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... CP2200/1 16.4. Multiplexed Motorola Format AS AD[7:0] /DS R/W Note: /CS must be asserted with or before /DS. Figure 28. Multiplexed Motorola READ AS AD[7:0] /DS R/W Note: /CS must be asserted with or before /DS. Figure 29. Multiplexed Motorola WRITE 102 T T AS1 AS2 VD1 Valid Address Valid Data T DSR T RWS T T AS1 AS2 ...
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... Hold Delay (Read/Write) HOLD Min Typ 40 — 40 — 40 — 40 — 40 — 160 — — — — 60 120 — 40 — 60 — 60 — 60 — Rev. 1.0 CP2200/1 Max UNITS — ns — ns — ns — ns — ns — ns 140 ns — ns — ns — ns — ns — ns — ns 103 ...
Page 104
... The Lot ID Code on the top side of the device package can be used for decoding device revision information. On CP220x devices, the revision letter is the first letter of the Lot ID Code. Figures 30 and 31 show how to find the Lot ID Code on the top side of the device package. Figure 30. Device Package—TQFP 48 104 CP2200 CCLZ9L This first character identifies the Silicon Revision S ILA B S ...
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... MAC address (where the only difference is in the 6th byte) on the same subnet managed switch network, present on most corporate LANs, the effect of this behavior is minimal due to the fact that the managed switch filters out unicast packets not addressed to the receiving Ethernet device. Rev. 1.0 CP2200/1 105 ...
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... CP2200 OCUMENT HANGE IST Revision 0.4 to Revision 0.41 Modified Figure 2, “Typical Connection Diagram (Non-Multiplexed),” on page 6 and Figure 3, “Typical Connection Diagram (Multiplexed),” on page 7 for improved EMI emmissions and common mode stability. Revision 0.41 to Revision 1.0 Added Maximum Supply Current specification in Table 2 on page 9. ...
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... N : OTES Rev. 1.0 CP2200/1 107 ...
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... CP2200 ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Email: MCUinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein ...