CP82C59AZ Intersil, CP82C59AZ Datasheet - Page 14

• Manufacturer Part Number: CP82C59AZ
• Description: IC INTERFACE 5V 8MHZ 28-DIP
• Manufacturer: Intersil

Specifications of CP82C59AZ

• Controller Type: CMOS Priority Interrupt Controller
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 1mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• Supply Voltage Range: 4.5V To 5.5V
• Supply Current: 1mA
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: Through Hole
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The difficulty here is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing a service routine), the
82C59A would have inhibited all lower priority requests with
no easy way for the routine to enable them.
That is where the Special Mask Mode comes in. In the
Special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupts
from all other levels (lower as well as higher) that are not
masked.
Thus, any interrupts may be selectively enabled by loading
the mask register.
The Special Mask Mode is set by OCW3 where: ESMM = 1,
SMM = 1, and cleared where ESMM = 1, SMM = 0.
Poll Command
In this mode, the INT output is not used or the
microprocessor internal Interrupt Enable flip flop is reset,
NOTES:
1. Master clear active only during ICW1.
2. FREEZE is active during INTA and poll sequence only.
3. Truth Table for D-latch.
8080/85
80C86/
88/286
MODE
MODE
C
1
0
IR
V
CC
FREEZE
FREEZE
INTA
INTA
D1
D
X
SENSE
LATCH
EDGE
CLR
SET
Q
1 = LEVEL
14
0 = EDGE
LTIM BIT
Qn-1
D1
Q
FREEZE
Operation
Follow
Hold
REQUEST
LATCH
D
C Q
TO OTHER PRIORITY CELLS
Q
READ
IRR
WRITE
MASK
82C59A
82C59A
MASK LATCH
D
C
CLR
Q
disabling its interrupt input. Service to devices is achieved by
software using a Poll command.
The Poll command is issued by setting P = 1 in OCW3. The
82C59A treats the next RD pulse to the 82C59A (i.e., RD =
0, CS = 0) as an interrupt acknowledge, sets the appropriate
IS bit if there is a request, and reads the priority level.
Interrupt is frozen from WR to RD.
The word enabled onto the data bus during RD is:
W0 - W2: Binary code of the highest priority level request-
I:
This mode is useful if there is a routine command common to
several levels so that the INTA sequence is not needed
(saves ROM space). Another application is to use the poll
mode to expand the number of priority levels to more than 64.
D7
I
D6
-
ing service.
Equal to a “1” if there is an interrupt.
IN - SERVICE
READ IMR
READ ISR
MASTER CLEAR
LATCH
CLR
SET
D5
-
Q
D4
-
NON-
MASKED
REQ
CLR ISR
ISR BIT
SET ISR
D3
-
W2
D2
PRIORITY
RESOLVER
CONTROL
LOGIC
W1
D1
March 17, 2006
FN2784.5
W0
D0