KSZ8873MLL AM Micrel Inc, KSZ8873MLL AM Datasheet - Page 87
![IC ETHERNET SWITCH 3PORT 64-LQFP](/photos/6/81/68149/64-lqfp-micrel_sml.jpg)
KSZ8873MLL AM
Manufacturer Part Number
KSZ8873MLL AM
Description
IC ETHERNET SWITCH 3PORT 64-LQFP
Manufacturer
Micrel Inc
Specifications of KSZ8873MLL AM
Controller Type
Ethernet Switch Controller
Interface
MII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Not Compliant, Lead free / RoHS Compliant
Other names
576-3633
KSZ8873MLL AM
KSZ8873MLLAM
KSZ8873MLL AM
KSZ8873MLLAM
Micrel, Inc.
“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters
are shown in the following table:
Examples:
Additional MIB Counter Information
“Per Port” MIB counters are designed as “read clear.” These counters will be cleared after they are read.
“All Port Dropped Packet” MIB counters are not cleared after they are accessed and do not indicate overflow or validity;
therefore, the application must keep track of overflow and valid conditions.
To read out all the counters, the best performance over the SPI bus is (160+3)*8*200 = 260ms, where there are 160
registers, 3 overheads, 8 clocks per access, at 5MHz. In the heaviest condition, the counters will overflow in 2 minutes. It
is recommended that the software read all the counters at least every 30 seconds.
A high performance SPI master is also recommended to prevent counters overflow.
September 2010
1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)
2. MIB Counter Read (Read port 2 “Rx64Octets” Counter)
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Then
Then,
Then
Write to reg. 121 (0x79) with 0x1c
Write to reg. 122 (0x7A) with 0x0e
Read reg. 128 (0x80), overflow bit [31]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Write to reg. 121 (0x79) with 0x1c
Write to reg. 122 (0x7A) with 0x2e
Read reg. 128 (0x80), overflow bit [31]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Write to reg. 121 (0x79) with 0x1d
Write to reg. 122 (0x7A) with 0x00
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
Offset
0x100
0x101
0x102
0x103
0x104
0x105
Table 21. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets
Port1 TX Drop Packets
Port2 TX Drop Packets
Port3 TX Drop Packets
Port1 RX Drop Packets
Port2 RX Drop Packets
Port3 RX Drop Packets
Counter Name
valid bit [30]
counter bits [29:24]
valid bit [30]
counter bits [29:24]
// Read MIB counters selected
// Trigger the read operation
// Read MIB counter selected
// Trigger the read operation
// Read MIB counter selected
// Trigger the read operation
Description
TX packets dropped due to lack of resources
TX packets dropped due to lack of resources
TX packets dropped due to lack of resources
RX packets dropped due to lack of resources
RX packets dropped due to lack of resources
RX packets dropped due to lack of resources
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
87
KSZ8873MLL/FLL/RLL
M9999-092309-1.2