PCA9665PW/S911,118 NXP Semiconductors, PCA9665PW/S911,118 Datasheet - Page 67
PCA9665PW/S911,118
Manufacturer Part Number
PCA9665PW/S911,118
Description
IC CNTRLR PARALLEL/I2C 20TSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9665PWS911118.pdf
(90 pages)
Specifications of PCA9665PW/S911,118
Controller Type
I²C Bus Controller
Interface
I²C
Voltage - Supply
2.3 V ~ 3.6 V
Current - Supply
100µA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935285487118
PCA9665PW/S911-T
PCA9665PW/S911-T
PCA9665PW/S911-T
PCA9665PW/S911-T
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NXP Semiconductors
PCA9665_3
Product data sheet
Fig 31. System configuration
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 32. Acknowledgement on the I
RECEIVER
SLAVE
SCL from master
by transmitter
data output
by receiver
data output
TRANSMITTER/
Rev. 03 — 12 August 2008
RECEIVER
condition
START
SLAVE
S
2
C-bus
TRANSMITTER
1
MASTER
2
Fm+ parallel bus to I
TRANSMITTER/
RECEIVER
MASTER
acknowledgement
not acknowledge
SLAVE
clock pulse for
acknowledge
8
MULTIPLEXER
PCA9665
© NXP B.V. 2008. All rights reserved.
002aaa987
2
I
2
9
C-bus controller
C-BUS
002aaa966
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