ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 67
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
ENC28J60-I/SS
Manufacturer Part Number
ENC28J60-I/SS
Description
IC ETHERNET CTRLR W/SPI 28SSOP
Manufacturer
Microchip Technology
Datasheet
1.ENC28J60SS.pdf
(98 pages)
Specifications of ENC28J60-I/SS
Package / Case
28-SSOP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
2.25 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current (max)
180 mA
Package
28SSOP
Standard Supported
IEEE 802.3
Communication Mode
Full Duplex|Half Duplex
Network Interface
MII|MIIM
Data Rate
10 Mbps
Host Interface
SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC28J60-I/SS
Manufacturer:
MURATA
Quantity:
30 000
REGISTER 12-2:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
INTIE
INTIE: Global INT Interrupt Enable bit
1 = Allow interrupt events to drive the INT pin
0 = Disable all INT pin activity (pin is continuously driven high)
PKTIE: Receive Packet Pending Interrupt Enable bit
1 = Enable receive packet pending interrupt
0 = Disable receive packet pending interrupt
DMAIE: DMA Interrupt Enable bit
1 = Enable DMA interrupt
0 = Disable DMA interrupt
LINKIE: Link Status Change Interrupt Enable bit
1 = Enable link change interrupt from the PHY
0 = Disable link change interrupt
TXIE: Transmit Enable bit
1 = Enable transmit interrupt
0 = Disable transmit interrupt
Reserved: Maintain as ‘0’
TXERIE: Transmit Error Interrupt Enable bit
1 = Enable transmit error interrupt
0 = Disable transmit error interrupt
RXERIE: Receive Error Interrupt Enable bit
1 = Enable receive error interrupt
0 = Disable receive error interrupt
R/W-0
PKTIE
EIE: ETHERNET INTERRUPT ENABLE REGISTER
W = Writable bit
‘1’ = Bit is set
DMAIE
R/W-0
LINKIE
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
TXIE
R/W-0
r
x = Bit is unknown
ENC28J60
TXERIE
R/W-0
DS39662C-page 65
RXERIE
R/W-0
bit 0