ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 24

• Manufacturer Part Number: ENC28J60-I/SS
• Description: IC ETHERNET CTRLR W/SPI 28SSOP
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SS

• Package / Case: 28-SSOP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 2.25 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current (max): 180 mA
• Package: 28SSOP
• Standard Supported: IEEE 802.3
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII|MIIM
• Data Rate: 10 Mbps
• Host Interface: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ENC28J60
3.3.4
The PHSTAT1 and PHSTAT2 registers contain read-
only bits that show the current status of the PHY
module’s operations, particularly the conditions of the
communications link to the rest of the network.
The PHSTAT1 register (Register 3-5) contains the
LLSTAT bit; it clears and latches low if the physical
layer link has gone down since the last read of the
register. Periodic polling by the host controller can be
used to determine exactly when the link fails. It may be
particularly useful if the link change interrupt is not
used.
The PHSTAT1 register also contains a jabber status bit.
An Ethernet controller is said to be “jabbering” if it con-
tinuously transmits data without stopping and allowing
other nodes to share the medium. Generally, the jabber
condition indicates that the local controller may be
grossly violating the maximum packet size defined by
the IEEE specification. This bit latches high to indicate
that a jabber condition has occurred since the last read
of the register.
The PHSTAT2 register (Register 3-6) contains status
bits which report if the PHY module is linked to the
network and whether or not it is transmitting or
receiving.
DS39662C-page 22
PHSTAT REGISTERS
Preliminary
3.3.5
The PHID1 and PHID2 registers are read-only
registers. They hold constant data that helps identify
the Ethernet controller and may be useful for
debugging purposes. This includes:
• The part number of the PHY module
• The revision level of the PHY module
• The PHY identifier, as part of Microchip’s
The PHY part number and revision are part of PHID2.
The upper two bytes of the PHY identifier are located in
PHID1, with the remainder in PHID2. The exact
locations within registers are shown in Table 3-3.
The 22 bits of the OUI contained in the PHY Identifier
(OUI3:OUI24, corresponding to PHID1<15:0> and
PHID2<15:10>) are concatenated with ‘00’ as the first
two digits (OUI1 and OUI2) to generate the entire OUI.
For convenience, this 24-bit string is usually interpreted
in hexadecimal; the resulting OUI for Microchip
Technology is 0004A3h.
Revision information is also stored in EREVID. This is
a read-only control register which contains a 5-bit
identifier for the specific silicon revision level of the
device. Details of this register are shown in Table 3-2.
(PPN5:PPN0)
(PREV3:PREV0); and
corporate Organizationally Unique Identifier (OUI)
(OUI3:OUI24)
PHID1 AND PHID2 REGISTERS
© 2008 Microchip Technology Inc.