CS82C59AZ Intersil, CS82C59AZ Datasheet - Page 8

• Manufacturer Part Number: CS82C59AZ
• Description: IC INTERRUPT CONTROLLER 28-PLCC
• Manufacturer: Intersil

Specifications of CS82C59AZ

• Controller Type: CMOS Priority Interrupt Controller
• Interface: System Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 1mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
During the third INTA pulse, the higher address of the
appropriate service routine, which was programmed as byte 2
of the initialization sequence (A8 - A15), is enabled onto the
bus.
80C86, 8OC88, 80C286 Interrupt Response Mode
80C86/88/286 mode is similar to 8080/85 mode except that
only two Interrupt Acknowledge cycles are issued by the
processor and no CALL opcode is sent to the processor. The
first interrupt acknowledge cycle is similar to that of 8080/85
systems in that the 82C59A uses it to internally freeze the
state of the interrupts for priority resolution and, as a master,
it issues the interrupt code on the cascade lines. On this first
cycle, it does not issue any data to the processor and leaves
its data bus buffers disabled. On the second interrupt
acknowledge cycle in the 86/88/286 mode, the master (or
A15
IR
IR
D7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CONTENT OF SECOND INTERRUPT VECTOR BYTE
CONTENT OF THIRD INTERRUPT VECTOR BYTE
D7
D7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A14
D6
D6
D6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A13
D5
DS
D5
A5
A5
A5
A5
A5
A5
A5
A5
1
1
1
1
0
0
0
0
A12
D4
INTERVAL = 8
INTERVAL = 4
D4
D4
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
8
A11
D3
D3
D3
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
A10
D2
D2
D2
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
D1
A9
D1
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D0
A8
D0
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
82C59A
82C59A
slave if so programmed) will send a byte of data to the
processor with the acknowledged interrupt code composed
as follows (note the state of the ADI mode control is ignored
and A5 - A11 are unused in the 86/88/286 mode).
Programming the 82C59A
The 82C59A accepts two types of command words
generated by the CPU:
1. Initialization Command Words (ICWs): Before normal
2. Operation Command Words (OCWs): These are the
The OCWs can be written into the 82C59A anytime after
initialization.
Initialization Command Words (lCWs)
General
Whenever a command is issued with A0 = 0 and D4 = 1, this
is interpreted as Initialization Command Word 1 (lCW1).
lCW1 starts the initialization sequence during which the
following automatically occur:
a. The edge sense circuit is reset, which means that follow-
b. The Interrupt Mask Register is cleared.
c. lR7 input is assigned priority 7.
d. Special Mask Mode is cleared and Status Read is set to
IR5
IR4
IR3
IR2
IR1
IR0
lR7
lR6
operation can begin, each 82C59A in the system must be
brought to a starting point - by a sequence of 2 to 4 bytes
timed by WR pulses.
command words which command the 82C59A to operate
in various interrupt modes. Among these modes are:
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
ing initialization, an interrupt request (IR) input must make
a low-to-high transition to generate an interrupt.
lRR.
CONTENT OF INTERRUPT VECTOR BYTE FOR
D7
T7
T7
T7
T7
T7
T7
T7
T7
D6
T6
T6
T6
T6
T6
T6
T6
T6
80C86/88/286 SYSTEM MODE
D5
T5
T5
T5
T5
T5
T5
T5
T5
D4
T4
T4
T4
T4
T4
T4
T4
T4
D3
T3
T3
T3
T3
T3
T3
T3
T3
D2
1
1
1
1
0
0
0
0
D1
March 17, 2006
1
1
0
0
1
1
0
0
FN2784.5
D0
1
0
1
0
1
0
1
0