Z8523016VSG Zilog, Z8523016VSG Datasheet - Page 27

• Manufacturer Part Number: Z8523016VSG
• Description: IC 16MHZ ESCC 44-PLCC
• Manufacturer: Zilog

Specifications of Z8523016VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3927; Z8523016VSG

Z80230/Z85230 Enhancements
PS005303-0907
4-Byte Transmit FIFO Buffer
8-Byte Receive FIFO
A detailed description of the enhancements to the Z80230/Z85230 ESCC that differentiate
it from the standard SCC is provided below:
The ESCC has a 4-byte transmit buffer with programmable interrupt and DMA request
levels. It is not necessary to enable the FIFO buffer as it is always available. You can set
the Transmit Buffer Empty (TBE) interrupt and DMA Request on Transmit command to
be generated either when the top byte of transmit FIFO is empty or only when the FIFO is
completely empty. A hardware or channel reset clears the transmit shift register, flushes
the transmit FIFO, and sets WR7’ bit 5 to 1.
If the transmitter generates the interrupt or DMA request for data when the top byte of the
FIFO is empty (WR7’ bit 5 is 0), the system allows for a long response time to the data
request without underflowing. The interrupt service routine (ISR) writes one byte and then
tests RR0 bit 2. The DMA Request on Transmit in this mode is set to 0 after each data
Write (that is, TBE), RR0 bit 2, is set to 1 when the top byte of the FIFO is empty. WR7’
bit 5 resets to 1.
In applications for which the interrupt frequency is important, the transmit ISR can be
optimized by programming the ESCC to generate the TBE interrupt only when the FIFO is
completely empty (WR7’ bit 5 is 1) and, writing four bytes to fill the FIFO. When WR7’
bit 5 is 1, only one DMA request is generated, filling the bottom of the FIFO. However,
this may be advantageous for applications where the possible reassertion of the DMA
request is not required. The TBE status bit, RR0 bit 2, is set to 1 when the top byte of the
FIFO is empty. WR7’ bit 5 is set to1 after a hardware or channel reset.
The ESCC has an 8-byte receive FIFO with programmable interrupt levels. It is not neces-
sary to enable the 8-byte FIFO as it is always available. A hardware or channel reset clears
the Receive Shift register and flushes the Receive FIFO. The Receive Character Available
interrupt is generated as selected by WR7’ bit 3. The Receive Character Available bit,
RR0 bit 0 is set to 1 when at least one byte is available at the top of the FIFO (independent
of WR7’ bit 3).
A DMA Request on Receive, if enabled, is generated whenever one byte is available in the
receive FIFO independent of WR7’ bit 3. If more than one byte is available in the FIFO,
the Wait/Request pin becomes inactive and becomes active when the FIFO is emptied.
Z80230/Z85230 Enhancements
Product Specification
Z85230/Z80230
22