CY7C68033-56LFXC Cypress Semiconductor Corp, CY7C68033-56LFXC Datasheet - Page 31

• Manufacturer Part Number: CY7C68033-56LFXC
• Description: IC USB NX2LP NAND CNTRLR 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68033-56LFXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• No. Of I/o's: 12
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Digital Ic Case Style: QFN
• Supply Voltage Range: 3V To 3.6V
• Core Size: 8 Bit
• Program Memory Size: 15KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 17
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
■
■
■
Sequence Diagram of a Single and Burst Asynchronous Write
Figure 19
in an asynchronous mode. The diagram shows a single write
followed by a burst write of three bytes and committing the
4-byte-short packet using PKTEND.
■
■
■
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
Document Number: 001-04247 Rev. *H
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of t
t
SLRD or before SLRD is asserted (that is the SLCS and SLRD
signals must both be asserted to start a valid read condition).
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of t
(SLCS may be tied low in some applications).
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
t
or before SLWR is asserted.
At t = 2, data must be present on the bus t
deasserting edge of SLWR.
RDpwh
WRpwh
FIFOADR
PKTEND
FLAGS
SLWR
DATA
SLCS
. If SLCS is used then, SLCS must be in asserted with
. If the SLCS is used, it must be in asserted with SLWR
on page 30 shows the timing relationship of the SLAVE
shows the timing relationship of the SLAVE FIFO write
t=0
SFA
RDpwl
WRpwl
t
SFA
. If SLCS is used, it must also be asserted
t =1
and minimum deactive pulse width of
t
and minimum de-active pulse width of
WRpwl
t=2
Figure 19. Slave FIFO Asynchronous Write Sequence and Timing Diagram
t
SFD
t=3
N
t
t
FDH
WRpwh
t
FAH
t
XFLG
SFD
T=0
t
before the
SFA
T=1
t
WRpwl
T=2
t
SFD
T=3
t
N+1
FDH
t
WRpwh
T=4
■
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After SLRD is
asserted, the data from the FIFO is driven on the data bus (SLOE
must also be asserted) and then the FIFO pointer is
incremented.
The FIFO flag is also updated after t
edge of SLWR.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post
incremented.
As shown in
and SLWR is deasserted, the short 4-byte packet can be
committed to the host using the PKTEND. The external device
should be designed to not assert SLWR and the PKTEND signal
at the same time. It should be designed to assert the PKTEND
after SLWR is deasserted and met the minimum de-asserted
pulse width. The FIFOADDR lines are to be held constant during
the PKTEND assertion.
t
WRpwl
The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
of t
is the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
T=5
t
SFD
XFD
T=6
t
N+2
FDH
t
WRpwh
from the activating edge of SLRD. In
Figure 19
T=7
t
WRpwl
T=8
t
SFD
T=9
after the four bytes are written to the FIFO
CY7C68033, CY7C68034
t
t
N+3
WRpwh
FDH
[5]
t
XFLG
PEpwl
from the deasserting
t
XFLG
t
Page 31 of 38
PEpwh
Figure
t
FAH
17, data N
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