CS8900A-CQ3Z Cirrus Logic Inc, CS8900A-CQ3Z Datasheet - Page 24

• Manufacturer Part Number: CS8900A-CQ3Z
• Description: IC LAN ETHERNET CTLR 3V 100LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Single Chipr

Specifications of CS8900A-CQ3Z

• Package / Case: 100-LQFP
• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: ISA-BUS
• Voltage - Supply: 3V, 5V
• Current - Supply: 95mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 10BASE- 2 or 10BASE- 5 or 10BASE- F or 10BASE- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1163 - KIT EVAL FOR CS8900A
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1127

Bits 8 through 0 of the Group Header specify a
9-bit PacketPage Address. This address de-
fines the PacketPage register that will be load-
ed with the first word of configuration data from
the group. Bits B though 9 of the Group Head-
er are forced to 0, restricting the destination
address range to the first 512 bytes of Packet-
Page memory. Figure 4 shows the format of
the Group header.
3.4.5 Reset Configuration Block Check-
sum
A checksum is stored in the high byte position
of the word immediately following the last
group of data in the Reset Configuration Block.
(The EEPROM address of the checksum val-
ue can be determined by dividing the value
stored in the Link Byte by two). The checksum
value is the 2’s complement of the 8-bit sum
(any carry out of eighth bit is ignored) of all the
bytes in the Reset Configuration Block, ex-
cluding the checksum byte. This sum includes
the Reset Configuration Block header at ad-
dress 00h. Since the checksum is calculated
as the 2’s complement of the sum of all pre-
ceding bytes in the Reset Configuration Block,
a total of 0 should result when the checksum
value is added to the sum of the previous
bytes.
3.4.6 EEPROM Example
Table 7 shows an example of a Reset Config-
uration Block stored in a C46 EEPROM. Note
that little-endian word ordering is used, i.e., the
least significant word of a multiword datum is
located at the lowest address.
3.4.7 EEPROM Read-out
If the EEDI pin is asserted high at the end of
reset, the CS8900A reads the first word of EE-
PROM data by:
1) Asserting EECS
2) Clocking out a Read-Register-00h com-
24
CIRRUS LOGIC PRODUCT DATASHEET
3) Clocking the data in on EEDI.
If the EEDI pin is low at the end of the reset sig-
nal, the CS8900A does not perform an EE-
PROM
configuration).
3.4.7.1 Determining EEPROM Size
The CS8900A determines the size of the EE-
PROM by checking the sense of EEDI on the
tenth rising edge of EESK. If EEDI is low, the
EEPROM is a ’C46 or ’CS46. If EEDI is high,
the EEPROM is a ’C56, ’CS56, ’C66, or ’CS66.
3.4.7.2 Loading Configuration Data
The CS8900A reads in the first word from the
EEPROM to determine if configuration data is
contained in the EEPROM. If configuration
data is not stored in the EEPROM, the
CS8900A terminates initialization from EE-
PROM and operates using its default configu-
ration (See Table 4). If configuration data is
stored in EEPROM, the CS8900A automati-
cally loads all configuration data stored in the
Reset Configuration Block into its internal
PacketPage registers.
3.4.8 EEPROM Read-out Completion
Once all the configuration data are transferred
to the appropriate PacketPage registers, the
CS8900A performs a checksum calculation to
verify the Reset Configuration Blocks data are
valid. If the resulting total is 0, the read-out is
considered valid. Otherwise, the CS8900A ini-
tiates a partial reset to restore the default con-
figuration.
If the read-out is valid, the EEPROMOK bit
(Register 16, SelfST, bit A) is set. EEPRO-
MOK is cleared if a checksum error is detect-
ed. In this case, the CS8900A performs a
partial reset and is restored to its default. Once
mand on EEDO (EESK provides a 1MHz
serial clock signal)
read-out
Crystal LAN™ Ethernet Controller
(uses
its
CS8900A
DS271F5
default