CS8900A-CQ3Z Cirrus Logic Inc, CS8900A-CQ3Z Datasheet - Page 17

• Manufacturer Part Number: CS8900A-CQ3Z
• Description: IC LAN ETHERNET CTLR 3V 100LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Single Chipr

Specifications of CS8900A-CQ3Z

• Package / Case: 100-LQFP
• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: ISA-BUS
• Voltage - Supply: 3V, 5V
• Current - Supply: 95mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 10BASE- 2 or 10BASE- 5 or 10BASE- F or 10BASE- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1163 - KIT EVAL FOR CS8900A
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1127

DS271F5
3.0 FUNCTIONAL DESCRIPTION
3.1 Overview
During normal operation, the CS8900A per-
forms two basic functions: Ethernet packet
transmission and reception. Before transmis-
sion or reception is possible, the CS8900A
must be configured.
3.1.1 Configuration
The CS8900A must be configured for packet
transmission and reception at power-up or re-
set. Various parameters must be written into
its internal Configuration and Control registers
such as Memory Base Address; Ethernet
Physical Address; what frame types to re-
ceive; and which media interface to use. Con-
figuration data can either be written to the
CS8900A by the host (across the ISA bus), or
loaded automatically from an external EE-
PROM. Operation can begin after configura-
tion is complete.
Section 3.3 on page 19 and Section 3.4 on
page 21 describe the configuration process in
detail. Section 4.4 on page 49 provides a de-
tailed description of the bits in the Configura-
tion and Control Registers.
3.1.2 Packet Transmission
Packet transmission occurs in two phases. In
the first phase, the host moves the Ethernet
frame into the CS8900A’s buffer memory. The
first phase begins with the host issuing a
Transmit
CS8900A that a frame is to be transmitted and
tells the chip when to start transmission (i.e. af-
ter 5, 381, 1021 or all bytes have been trans-
ferred) and how the frame should be sent (i.e.
with or without CRC, with or without pad bits,
etc.). The Host follows the Transmit Command
with the Transmit Length, indicating how much
buffer space is required. When buffer space is
available, the host writes the Ethernet frame
CS8900A
Crystal LAN™ Ethernet Controller
Command.
This
CIRRUS LOGIC PRODUCT DATASHEET
informs
the
into the CS8900A’s internal memory, either as
a Memory or I/O space operation.
In the second phase of transmission, the
CS8900A converts the frame into an Ethernet
packet then transmits it onto the network. The
second phase begins with the CS8900A trans-
mitting the preamble and Start-of-Frame de-
limiter as soon as the proper number of bytes
has been transferred into its transmit buffer (5,
381, 1021 bytes or full frame, depending on
configuration). The preamble and Start-of-
Frame delimiter are followed by the Destina-
tion Address, Source Address, Length field
and LLC data (all supplied by the host). If the
frame is less than 64 bytes, including CRC, the
CS8900A adds pad bits if configured to do so.
Finally, the CS8900A appends the proper 32-
bit CRC value.
The Section 5.6 on page 99 provides a de-
tailed description of packet transmission.
3.1.3 Packet Reception
Like packet transmission, packet reception oc-
curs in two phases. In the first phase, the
CS8900A receives an Ethernet packet and
stores it in on-chip memory. The first phase of
packet reception begins with the receive frame
passing through the analog front end and
Manchester decoder where Manchester data
is converted to NRZ data. Next, the preamble
and Start-of-Frame delimiter are stripped off
and the receive frame is sent through the ad-
dress filter. If the frame’s Destination Address
matches the criteria programmed into the ad-
dress filter, the packet is stored in the
CS8900A’s internal memory. The CS8900A
then checks the CRC, and depending on the
configuration, informs the processor that a
frame has been received.
In the second phase, the host transfers the re-
ceive frame across the ISA bus and into host
memory. Receive frames can be transferred
17