VNC1L-1A-REEL FTDI, Future Technology Devices International Ltd, VNC1L-1A-REEL Datasheet - Page 18

• Manufacturer Part Number: VNC1L-1A-REEL
• Description: IC USB HOST CTLR VINCULUM 48LQFP
• Manufacturer: FTDI, Future Technology Devices International Ltd
• Series: Vinculumr

Specifications of VNC1L-1A-REEL

• Controller Type: USB 2.0 Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: 768-1006 - BOARD DEV FOR VINCULUM VNC1L-1A768-1005 - MOD USB FLASH DISK FILE TRANSFER768-1002 - MOD MCU-USB HOST CTLR 40-DIP768-1001 - MOD MCU-USB HOST CTLR 24-DIP27937 - MEMORY STICK DATALOGGER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 768-1000-2

Table 5.6 SPI Master Data Read Status Bit
Figure 5.4 SPI Master Data Read (VNC1L Slave Mode)
The status bit is only valid until the next rising edge of SCLK after the last data bit.
During the Data Read operation the CS signal must not be de-asserted.
The transfer completes after 13 clock cycles and the next transfer can begin when SDI and CS are high
during the rising edge of SCLK.
5.2.3 SPI Master Data Transaction
During an SPI master Data Write operation the Start and Setup sequence is sent by the SPI master to
VNC1L, see Figure 5.5. This is followed by the SPI master transmitting each bit of the data to be written
to VNC1L. The VNC1L then responds with a status bit on SDO on the rising edge of the next clock cycle.
The SPI master must read the status bit at the end of each write transaction to determine if the data was
written successfully to VNC1L Receive Buffer. The Data Write status bit is defined in Table 5.7. The status
bit is only valid until the next rising edge of SCLK after the last data bit.
If the status bit indicates Accept then the byte transmitted has been added to VNC1L Receive Buffer. If it
shows Reject then the Receive Buffer is full and the byte of data transmitted in the current transaction
should be re-transmitted by the SPI master to VNC1L.
Any application should poll VNC1L Receive Buffer by retrying the Data Write operation until the data is
accepted.
Table 5.7 SPI Master Data Write Status Bit
Status Bit
Status Bit
0
1
0
1
Meaning
New Data
Old Data
Meaning
Accept
Reject
Copyright © 2009 Future Technology Devices International Limited
Data in current transaction is valid data.
Byte removed from Transmit Buffer.
This same data has been read in a previous read cycle.
Repeat the read cycle until New Data is received.
Vinculum VNC1L Embedded USB Host Controller IC Datasheet Version 2.02
Data from the current transaction was accepted and added to the Receive Buffer
Write data was not accepted.
Retry the same write cycle.
Document Reference No.: FT_000030
Clearance No.: FTDI# 50
18