ENC28J60-I/SP Microchip Technology, ENC28J60-I/SP Datasheet - Page 29
![IC ETHERNET CTRLR W/SPI 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
ENC28J60-I/SP
Manufacturer Part Number
ENC28J60-I/SP
Description
IC ETHERNET CTRLR W/SPI 28DIP
Manufacturer
Microchip Technology
Specifications of ENC28J60-I/SP
Package / Case
28-DIP (0.300", 7.62mm)
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Input Voltage Range (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
Through Hole
Operating Supply Voltage
3.1 V to 3.6 V
Supply Current (max)
180 mA
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps
Ethernet Connection Type
10Base-T
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC28J60-I/SP
Manufacturer:
MICROCHIP
Quantity:
6 500
4.2.1
The Read Control Register (RCR) command allows the
host controller to read any of the ETH, MAC and MII
registers in any order. The contents of the PHY regis-
ters are read via a special MII register interface (see
Section 3.3.1 “Reading PHY Registers” for more
information).
The RCR command is started by pulling the CS pin low.
The RCR opcode is then sent to the ENC28J60,
followed by a 5-bit register address (A4 through A0).
The 5-bit address identifies any of the 32 control
FIGURE 4-3:
FIGURE 4-4:
© 2006 Microchip Technology Inc.
SCK
SCK
CS
SO
CS
SO
SI
SI
READ CONTROL REGISTER
COMMAND
0
0
0
0
Opcode
High-Impedance State
Opcode
High-Impedance State
1
0
0
1
READ CONTROL REGISTER COMMAND SEQUENCE (ETH REGISTERS)
READ CONTROL REGISTER COMMAND SEQUENCE
(MAC AND MII REGISTERS)
0
2
0
3
4
2
4
3
Address
4
3
5
2
3
6
4
1
Address
0
7
2
5
7
8
1
6
6
9 10 11 12 13 14 15 16 17 18 19 20 21 22
Preliminary
0
5
Dummy Byte
7
4
7
8
3
registers in the current bank. If the 5-bit address is an
ETH register, then data in the selected register will
immediately start shifting out MSb first on the SO pin.
Figure 4-3 shows the read sequence for these
registers.
If the address specifies one of the MAC or MII registers,
a dummy byte will first be shifted out the SO pin. After
the dummy byte, the data will be shifted out MSb first
on the SO pin. The RCR operation is terminated by
raising the CS pin. Figure 4-4 shows the read
sequence for MAC and MII registers.
2
6
9
1
5
10
0
Data Out
4
7
11
6
3
12
Data Byte Out
5
2
4
13
ENC28J60
3
1
14
2
0
15
1
DS39662B-page 27
23
0