ENC28J60/SS Microchip Technology, ENC28J60/SS Datasheet
ENC28J60/SS
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ENC28J60/SS Summary of contents
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... Microchip Technology Inc. Stand-Alone Ethernet Controller with SPI Interface Preliminary ENC28J60 Data Sheet DS39662C ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Physical Layer (PHY) Features • Loopback mode • Two Programmable LED Outputs for LINK, TX, RX, Collision and Full/Half-Duplex Status © 2008 Microchip Technology Inc. ENC28J60 Operational • Six Interrupt Sources and One Interrupt Output Pin • 25 MHz Clock Input Requirement • ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39662C-page 2 Preliminary © 2008 Microchip Technology Inc. ...
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... SI SPI SO (1) SCK Note 1: These pins are 5V tolerant. © 2008 Microchip Technology Inc. The ENC28J60 consists of seven major functional blocks SPI interface that serves as a communica- tion channel between the host controller and the ENC28J60. 2. Control registers which are used to control and monitor the ENC28J60 ...
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... Ground reference for oscillator. ANA Oscillator input. — Oscillator output. — Positive 3.3V supply for oscillator. (5) — LEDB driver pin. (5) — LEDA driver pin. — Positive 3.3V supply Preliminary TPIN+/- RJ45 TPOUT+/- ETHERNET TRANSFORMER LEDA LEDB (3,4) © 2008 Microchip Technology Inc. ...
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... Note 1: Duty cycle restrictions must be observed resistor to ground may be used to reduce system noise. This may increase system current. © 2008 Microchip Technology Inc. 2.2 Oscillator Start-up Timer The ENC28J60 contains an Oscillator Start-up Timer (OST) to ensure that the oscillator and integrated PHY have stabilized before use. The OST does not expire until 7500 OSC1 clock cycles (300 μ ...
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... Figure 2-3). During this period, CLKOUT will be held low. U-0 U-0 R/W-1 — — COCON2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. R/W-0 R/W-0 COCON1 COCON0 bit Bit is unknown ...
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... Required only if the microcontroller is operating at 5V. See Section 2.5 “I/O Levels” for more information. 3: These components are installed for EMI reduction purposes. © 2008 Microchip Technology Inc. A common-mode choke on the TPOUT interface, placed between the TPOUT pins and the Ethernet transformer (not shown), is not recommended ...
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... LACFG3:LACFG0 and LBCFG3:LBCFG0 bits. Typical values for blink stretch are listed in Table 2-1. TABLE 2-1: Stretch Length T (normal) NSTRCH T (medium) MSTRCH T (long) LSTRCH Preliminary LEDB POLARITY AND RESET CONFIGURATION OPTIONS +3. LED BLINK STRETCH LENGTH Typical Stretch (ms 140 © 2008 Microchip Technology Inc. ...
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... STRCH: LED Pulse Stretching Enable bit 1 = Stretchable LED events will cause lengthened LED pulses based on LFRQ1:LFRQ0 configuration 0 = Stretchable LED events will only be displayed while they are occurring bit 0 Reserved: Write as ‘0’ © 2008 Microchip Technology Inc. R/W-1 R/W-0 R/W-1 r LACFG3 ...
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... ENC28J60 NOTES: DS39662C-page 10 Preliminary © 2008 Microchip Technology Inc. ...
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... Note: Memory areas are not shown to scale. The size of the control memory space has been scaled to show detail. © 2008 Microchip Technology Inc. The Ethernet buffer contains transmit and receive memory used by the Ethernet controller in a single memory space. The sizes of the memory areas are programmable by the host controller using the SPI interface ...
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... EREVID 13h — 14h — 15h ECOCON 16h Reserved 17h EFLOCON 18h EPAUSL 19h EPAUSH 1Ah Reserved 1Bh EIE 1Ch EIR 1Dh ESTAT 1Eh ECON2 1Fh ECON1 © 2008 Microchip Technology Inc. ...
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... Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets. 2: EREVID is a read-only register. 3: ECOCON resets to ‘---- -100’ on Power-on Reset and ‘---- -uuu’ on all other Resets. © 2008 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 DMAIE LINKIE ...
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... TME BISTST 75 0000 0000 76 0000 0000 76 0000 0000 SCAN BUSY 21 ---- 0000 ---q qqqq 22 COCON1 COCON0 6 ---- -100 FCEN1 FCEN0 56 ---- -000 57 0000 0000 57 0001 0000 © 2008 Microchip Technology Inc. ...
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... All packets received will be ignored bit 1-0 BSEL1:BSEL0: Bank Select bits 11 = SPI accesses registers in Bank SPI accesses registers in Bank SPI accesses registers in Bank SPI accesses registers in Bank 0 © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 CSUMEN TXRTS RXEN U = Unimplemented bit, read as ‘0’ ...
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... Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared once it is set. DS39662C-page 16 R/W-0 R/W-0 U-0 r VRPS — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. 3.2.2 TRANSMIT BUFFER Any space within the 8-Kbyte memory, which is not programmed as part of the receive FIFO buffer, is considered to be the transmit buffer ...
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... Transmit Buffer End (ETXNDH:ETXNDL) Receive Buffer Start (ERXSTH:ERXSTL) Buffer Read Pointer (ERDPTH:ERDPTL) Receive Buffer End (ERXNDH:ERXNDL) DS39662C-page 18 0000h Transmit Buffer Data AAh (WBM AAh) Transmit Buffer Receive Buffer (Circular FIFO) Receive Buffer Data 55h (RBM 55h) 1FFFh Preliminary © 2008 Microchip Technology Inc. ...
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... necessary to reprogram only select bits in the register, the controller must first read the PHY register, modify the resulting data and then write the data back to the PHY register. © 2008 Microchip Technology Inc. To write to a PHY register: 1. Write the address of the PHY register to write to into the MIREGADR register ...
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... ENC28J60 DS39662C-page 20 Preliminary © 2008 Microchip Technology Inc. ...
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... SCAN: MII Management Scan Operation bit 1 = MII Management scan operation is in progress MII Management scan operation is in progress bit 0 BUSY: MII Management Busy bit PHY register is currently being read or written The MII Management interface is Idle © 2008 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
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... OUI for Microchip Technology is 0004A3h. Revision information is also stored in EREVID. This is a read-only control register which contains a 5-bit identifier for the specific silicon revision level of the device. Details of this register are shown in Table 3-2. Preliminary © 2008 Microchip Technology Inc. ...
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... JBSTAT: PHY Latching Jabber Status bit 1 = PHY has detected a transmission meeting the jabber criteria since PHSTAT1 was last read 0 = PHY has not detected any jabbering transmissions since PHSTAT1 was last read bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. R-1 R-1 U-0 PFDPX PHDPX — ...
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... Section 2.6 “LED Configuration” for additional details). DS39662C-page 24 R-0 R-0 R-0 RXSTAT COLSTAT LSTAT U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-x U-0 (1) DPXSTAT — bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... SCK SO MSb Out SI © 2008 Microchip Technology Inc. Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the ENC28J60 on the SO line, on the falling edge of SCK. The CS pin must be held low while any operation is performed and returned high when finished ...
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... Write and bit field instructions are also followed by one or more bytes of data. A total of seven instructions are implemented on the ENC28J60. Table 4-1 shows the command codes for all operations. Byte 0 Opcode Argument Preliminary Byte 1 and Following Data N/A N N/A © 2008 Microchip Technology Inc. ...
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... SI High-Impedance State SO © 2008 Microchip Technology Inc. registers in the current bank. If the 5-bit address is an ETH register, then data in the selected register will immediately start shifting out MSb first on the SO pin. Figure 4-3 shows the read sequence for these registers. If the address specifies one of the MAC or MII registers, a dummy byte will first be shifted out on the SO pin ...
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... If the CS line is allowed to go high before eight bits are loaded, the write will be aborted for that data byte. Refer to the timing diagram in Figure 4-5 for a more detailed illustration of the byte write sequence Address Data Byte High-Impedance State Preliminary © 2008 Microchip Technology Inc. ...
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... SI SO © 2008 Microchip Technology Inc. The BFS command is started by pulling the CS pin low. The BFS opcode is then sent, followed by a 5-bit address (A4 through A0). The 5-bit address identifies any of the ETH registers in the current bank. After the BFS command and address are sent, the data byte containing the bit field set information should be sent, MSb first ...
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... The SRC operation is terminated by raising the CS pin. Figure 4-7 shows a detailed illustration of the System Reset Command sequence. For more information on SRC’s Soft Reset, refer to Section 11.2 “System Reset” Data Constant (1Fh High-Impedance State Preliminary 7 1 © 2008 Microchip Technology Inc. ...
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... Used in the Calculation of the FCS 46-1500 4 Note 1: The FCS is transmitted starting with bit 31 and ending with bit 0. © 2008 Microchip Technology Inc. beginning of the Ethernet packet. Thus, traffic seen on the twisted-pair cabling will appear as shown in Figure 5-1. 5.1.1 PREAMBLE/START-OF-FRAME DELIMITER When transmitting and receiving data with the ...
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... Otherwise, the host controller must generate the CRC and place it in the transmit buffer. Given the com- plexity of calculating a CRC highly recommended that the PADCFG bits be configured such that the ENC28J60 will automatically generate the CRC field. Preliminary © 2008 Microchip Technology Inc. ...
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... ERXRDPT, the host controller must write to ERXRDPTL first, followed by ERXRDPTH. See Section 7.2.4 “Freeing Receive Buffer Space” for more information. © 2008 Microchip Technology Inc. 6.2 Transmit Buffer All memory which is not used by the receive buffer is considered the transmission buffer. Data which transmitted should be written into any unused space ...
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... MACLCON2 may need to be increased. 9. Program the local MAC address into the MAADR1:MAADR6 registers. R-0 R/W-0 R/W-0 r TXPAUS RXPAUS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PASSALL MARXEN bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Frame lengths will not be compared with the type/length field bit 0 FULDPX: MAC Full-Duplex Enable bit 1 = MAC will operate in Full-Duplex mode. PDPXMD bit must also be set MAC will operate in Half-Duplex mode. PDPXMD bit must also be clear. © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 TXCRCEN ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 BBIPG4 BBIPG3 BBIPG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0 R bit Bit is unknown R/W-0 R/W-0 BBIPG1 BBIPG0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Transmitted data will be looped back to the MAC and sent out on the twisted-pair interface bit 7-0 Reserved: Write as ‘0’ © 2008 Microchip Technology Inc. If using half duplex, the host controller may wish to set the PHCON2.HDLDIS bit to prevent automatic loopback of the data which is transmitted. ...
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... ENC28J60 NOTES: DS39662C-page 38 Preliminary © 2008 Microchip Technology Inc. ...
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... The values of PCRCEN, PPADEN and PHUGEEN will override the configuration defined by MACON3 0 = The values in MACON3 will be used to determine how the packet will be transmitted © 2008 Microchip Technology Inc. Additionally, the ENC28J60 requires a single per packet control byte to precede the packet for transmission. The per packet control byte is organized as shown in Figure 7-1 ...
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... ESTAT.LATECOL bit in addition to the various fields in the transmit status vector to determine the cause. The transmit status vector is organized as shown in Table 7-1. Multi-byte fields are written in little-endian format. Preliminary © 2008 Microchip Technology Inc. ...
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... Transmit CRC Error 19-16 Transmit Collision Count 15-0 Transmit Byte Count © 2008 Microchip Technology Inc. Description 0 Frame’s length/type field contained 8100h which is the VLAN protocol identifier. Carrier sense method backpressure was previously applied. The frame transmitted was a control frame with a valid pause opcode. ...
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... TX End High Byte (ETXND<12:8>) — r TXPAUS RXPAUS TXCRCEN PHDREN HFRMEN BPEN NOBKOFF — — — — Retransmission Maximum (RETMAX<3:0>) Preliminary Reset Bit 1 Bit 0 Values on page r TXERIE RXERIE 13 r TXERIF RXERIF 13 (1) TXABRT CLKRDY 13 BSEL1 BSEL0 PASSALL MARXEN 14 FRMLNEN FULDPX © 2008 Microchip Technology Inc. ...
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... Packet © 2008 Microchip Technology Inc. After reception is enabled, packets which are not filtered out will be written into the circular receive buffer. Any packet which does not meet the necessary filter criteria will be discarded and the host controller will not have any means of identifying that a packet was thrown away ...
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... ERDPT, taking care to not exceed the end of the receive buffer if the packet spans the ERXND-to-ERXST buffer boundary. In other words, given the packet start address and a desired offset, the application should Example 7-1. Preliminary follow the logic shown in © 2008 Microchip Technology Inc. ...
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... Free Space = (ERXND – ERXST) else Free Space = ERXRDPT – ERXWRPT – 1 © 2008 Microchip Technology Inc. Because only one pointer is available to control buffer area ownership, the host controller must process pack- ets in the order they are received. If the host controller wishes to save a packet to be processed later, it should copy the packet to an unused location in memory ...
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... MPEN HTEN — r TXPAUS RXPAUS PADCFG0 TXCRCEN PHDREN HFRMEN Preliminary Reset Bit 2 Bit 1 Bit 0 Values on page r TXERIE RXERIE 13 r TXERIF RXERIF 13 (1) TXABRT CLKRDY 13 — — — 13 BSEL1 BSEL0 MCEN BCEN 14 14 PASSALL MARXEN 14 FRMLNEN FULDPX © 2008 Microchip Technology Inc. ...
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... Magic Packet™ • Hash Table • Multicast • Broadcast © 2008 Microchip Technology Inc. The individual filters are all configured by the ERXFCON register (Register 8-1). More than one filter can be active at any given time. Additionally, the filters can be config- ured by the ANDOR bit to either logically AND, or logically OR, the tests of several filters ...
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... When ANDOR = Packets which have a destination address of FF-FF-FF-FF-FF-FF will be accepted 0 = Filter disabled DS39662C-page 48 R/W-0 R/W-0 R/W-0 PMEN MPEN HTEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-1 MCEN BCEN bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... No Yes Magic Packet™ MPEN set? No Yes Hash table HTEN set? No Yes MCEN set? destination? No Yes BCEN set? destination? No © 2008 Microchip Technology Inc. Yes Unicast CRCEN set? packet? No CRCEN valid? Yes Pattern matches? No Yes for us? No Yes bit set? No Yes ...
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... Magic Packet™ for us? No Yes Yes No Hash Table HTEN set? bit set? No Yes Yes No Multicast MCEN set? destination? No Yes Yes No Broadcast BCEN set? destination? No Yes No CRCEN set? Yes No CRC valid? Yes Accept Packet Reject Packet Preliminary © 2008 Microchip Technology Inc. ...
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... Note: Received data is shown in hexadecimal. Byte numbers are shown in decimal format. © 2008 Microchip Technology Inc. the filter criteria will immediately not be met, even if the corresponding mask bits are all ‘0’. The Pattern Match Checksum registers should be programmed to the checksum which is expected for the selected bytes ...
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... Multicast filter criteria. 8.6 Broadcast Filter The Broadcast receive filter checks the destination address of all incoming packets. If the destination address is FF-FF-FF-FF-FF-FF, the packet will meet the Broadcast filter criteria. Preliminary © 2008 Microchip Technology Inc. ...
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... ESTAT.TXABRT flag. For more information, see Section 7.1 “Transmitting Packets”. A transmit abort will cause the transmit error interrupt. © 2008 Microchip Technology Inc the collision occurs after the number of bytes specified MACLCON2 were transmitted, the packet will be immediately aborted without any retransmission attempts ...
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... ENC28J60 NOTES: DS39662C-page 54 Preliminary © 2008 Microchip Technology Inc. ...
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... The pause timer value will be extracted from the control frame and used to initialize an internal timer. The timer will auto- © 2008 Microchip Technology Inc. matically decrement every 512 bit times or 51.2 μs. While the timer is counting down, reception of packets is still enabled ...
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... MACON1 and then manually interpret the pause control frames which may arrive. U-0 U-0 R-0 — — FULDPXS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. will automatically inhibit host controller sets the R/W-0 R/W-0 FCEN1 ...
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... EFLOCON — — EPAUSL Pause Timer Value Low Byte (EPAUS<7:0>) EPAUSH Pause Timer Value High Byte (EPAUS<15:8>) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used. © 2008 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 DMAST CSUMEN TXRTS RXEN — ...
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... ENC28J60 NOTES: DS39662C-page 58 Preliminary © 2008 Microchip Technology Inc. ...
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... A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 11-1. FIGURE 11-1: ON-CHIP RESET CIRCUIT Soft Reset Command Hardware Reset POR Transmit Reset Receive Reset © 2008 Microchip Technology Inc. System Reset Reset Host Interface Reset Transmit Reset Receive Preliminary ENC28J60 DS39662C-page 59 ...
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... Receive Only Reset. Other register and control blocks, such as the buffer management and host interface blocks, are not affected by a Receive Only Reset event. When the host controller wishes RSTLOW return to normal operation, it should clear the RXRST bit. Preliminary © 2008 Microchip Technology Inc. ...
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... Reset values of the Duplex mode/status bits depend on the connection of the LED to the LEDB pin (see Section 2.6 “LED Configuration” for additional details). © 2008 Microchip Technology Inc. Unlike other Resets, the PHY cannot be removed from Reset immediately after setting PRST. The PHY requires a delay, after which the hardware automati- cally clears the PRST bit ...
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... ENC28J60 NOTES: DS39662C-page 62 Preliminary © 2008 Microchip Technology Inc. ...
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... PLNKIF PGIF PLNKIE PGEIE © 2008 Microchip Technology Inc. When an enabled interrupt occurs, the interrupt pin will remain low until all flags which are causing the interrupt are cleared or masked off (enable bit is cleared) by the host controller. If more than one interrupt source is enabled, the host controller must poll each flag in the EIR register to determine the source(s) of the interrupt ...
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... The registers associated with the INT interrupts are shown in Register 12-2, Register 12-3, Register 12-4 and Register 12-5. R/C-0 U-0 R-0 LATECOL — RXBUSY U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/C-0 R/W-0 (1) TXABRT CLKRDY bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... TXERIE: Transmit Error Interrupt Enable bit 1 = Enable transmit error interrupt 0 = Disable transmit error interrupt bit 0 RXERIE: Receive Error Interrupt Enable bit 1 = Enable receive error interrupt 0 = Disable receive error interrupt © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 LINKIE TXIE Unimplemented bit, read as ‘0’ ...
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... A packet was aborted because there is insufficient buffer space or the packet count is 255 receive error interrupt is pending DS39662C-page 66 R-0 R/C-0 R-0 LINKIF TXIF Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/C-0 R/C-0 TXERIF RXERIF bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... PGIF: PHY Global Interrupt Flag bit 1 = One or more enabled PHY interrupts have occurred since PHIR was last read; resets to ‘0’ when read PHY interrupts have occurred bit 1 Reserved: Do not modify bit 0 Reserved: Read as ‘0’ © 2008 Microchip Technology Inc. R-0 R-0 R ...
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... EIE.INTIE = 0), the host controller may poll the ENC28J60 for the TXIF bit and take appropriate action. Once processed, the host controller should use the BFC command to clear the EIR.TXIF bit. setting the per packet Preliminary © 2008 Microchip Technology Inc. ...
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... PLNKIF bits automatically and allow for future link status change interrupts. See Section 3.3 “PHY Registers” for information on accessing the PHY registers. © 2008 Microchip Technology Inc. 12.1.6 DMA INTERRUPT FLAG (DMAIF) The DMA interrupt indicates that the DMA module has completed its memory copy or checksum calculation (ECON1.DMAST has transitioned from ‘ ...
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... Put the host controller and other subsystems to Sleep to save power. Once a Magic Packet is received, the EPKTCNT is incremented to ‘1’, which causes the EIR.PKTIF bit to set. In turn, the ESTAT.INT bit is set and the INT signal options). is driven low, causing the host to wake-up. Preliminary © 2008 Microchip Technology Inc. ...
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... EDMAND). An attempt will overwrite all memory in the buffer and may never end. © 2008 Microchip Technology Inc. 13.1 Copying Memory To copy memory within the buffer: 1. Appropriately program the EDMAST, EDMAND and EDMADST register pairs. The EDMAST ...
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... RX End High Byte (ERXND<12:8>) — DMA Start High Byte (EDMAST<12:8>) — DMA End High Byte (EDMAND<12:8>) — DMA Destination High Byte (EDMADST<12:8>) Preliminary Reset Bit 1 Bit 0 Values on page r TXERIE RXERIE 13 r TXERIF RXERIF 13 BSEL1 BSEL0 © 2008 Microchip Technology Inc. ...
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... Legend: — = unimplemented, read as ‘0’ reserved bit. Shaded cells are not used for power-down. Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets. © 2008 Microchip Technology Inc. When normal operation is desired, the host controller must perform a slightly modified procedure: 1 ...
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... ENC28J60 NOTES: DS39662C-page 74 Preliminary © 2008 Microchip Technology Inc. ...
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... BISTST: Built-in Self-Test Start/Busy bit 1 = Test in progress; cleared automatically when test is done test running © 2008 Microchip Technology Inc. The BIST controller is operated through four registers: • EBSTCON register (control and status register) • EBSTSD register (fill seed/initial shift value) • ...
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... EBSTSD are wrapped around to the least significant side. This shift is repeated for each new address result of shifting the data, a checker- board pattern can be written into the buffer memory to confirm that adjacent memory elements do not affect each other when accessed. Preliminary © 2008 Microchip Technology Inc. ...
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... EBSTCON PSV2 PSV1 EBSTCSL Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) EBSTCSH Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used. © 2008 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 DMAST CSUMEN TXRTS RXEN — ...
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... ENC28J60 NOTES: DS39662C-page 78 Preliminary © 2008 Microchip Technology Inc. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. © 2008 Microchip Technology Inc. and V , with respect to V ...
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... -4.0 mA (Note RESET = ≤ V ≤ pins in SS PIN DD high-impedance state (Note 1) OSC1 = V (Note 3.30V MHz, DD SCK SO = Open, LEDA and LEDB Open, ECON2<PWRSV> 3.30V, DD LEDA and LEDB Open, ECON2<PWRSV> Inputs tied 3.3V 25°C, A ECON2<PWRSV> © 2008 Microchip Technology Inc. ...
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... REQUIREMENTS FOR EXTERNAL MAGNETICS Parameter RX Transformer Turns Ratio TX Transformer Turns Ratio Insertion Loss Primary Inductance Transformer Isolation Differential to Common Mode Rejection Return Loss © 2008 Microchip Technology Inc. Standard Operating Conditions -40°C ≤ T ≤ +85°C, 3.10V ≤ 0°C ≤ T ≤ +70°C, 3.10V ≤ ...
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... LSb Out Don’t Care Min Max Units DC 20 MHz 50 — — ns ETH registers and memory buffer 210 — ns MAC and MII registers 50 — — — ns — Load = 30 pF — Load = 30 pF Preliminary T CSD T DIS Conditions © 2008 Microchip Technology Inc. ...
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... Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. Example ENC28J60-I/SP 0810017 Example ...
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... ENC28J60 17.2 Package Details The following sections give the technical details of the packages. N NOTE DS39662C-page Preliminary © 2008 Microchip Technology Inc ...
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... D N NOTE © 2008 Microchip Technology Inc α h φ Preliminary ENC28J60 c β DS39662C-page 85 ...
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... ENC28J60 NOTE DS39662C-page Preliminary © 2008 Microchip Technology Inc. φ L ...
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... D TOP VIEW A3 © 2008 Microchip Technology Inc. EXPOSED PAD NOTE 1 BOTTOM VIEW A A1 Preliminary ENC28J60 DS39662C-page 87 ...
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... ENC28J60 DS39662C-page 88 Preliminary © 2008 Microchip Technology Inc. ...
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... APPENDIX A: REVISION HISTORY Revision A Original data sheet for the ENC28J60. Revision B (July 2006) Revision C (January 2008) Added one line to “Ethernet Controller Features” and added omitted revision history. Minor edits to text throughout document. © 2008 Microchip Technology Inc. Preliminary ENC28J60 DS39662C-page 89 ...
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... ENC28J60 NOTES: DS39662C-page 90 Preliminary © 2008 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2008 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39662C-page 92 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS39662C Preliminary . © 2008 Microchip Technology Inc. ...
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... EREVID Register ................................................................ 22 Errata .................................................................................... 2 Ethernet Buffer .................................................................... 17 Ethernet Module Transmitting and Receiving Data Receive Packet Layout ....................................... 43 Transmit Packet Layout ...................................... 40 Ethernet Overview .............................................................. 31 © 2008 Microchip Technology Inc. F Flow Control........................................................................ 55 Associated Registers.................................................. 57 Full-Duplex Mode ....................................................... 55 Half-Duplex Mode....................................................... 55 Sample Full-Duplex Network (Diagram) ..................... 55 Flowcharts Receive Filters Using AND Logic ............................... 50 Receive Filters Using OR Logic ...
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... Read Control Register Command (MAC/MII Registers) ........................................... 27 SPI Input ............................................................... 25, 82 SPI Output ............................................................ 25, 82 System Reset Command Sequence........................... 30 Write Buffer Memory Command Sequence ................ 29 Write Control Register Command Sequence.............. 28 Transmit Buffer ................................................................... 17 Transmitting Packets .......................................................... 39 Associated Registers .................................................. 42 Status Vectors ............................................................ 41 W WWW, On-Line Support ....................................................... 2 Preliminary © 2008 Microchip Technology Inc. ...
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... Package SP = SPDIP (Skinny Plastic DIP SOIC (Plastic Small Outline SSOP (Plastic Shrink Small Outline QFN (Quad Flat No Lead) © 2008 Microchip Technology Inc. Examples: a) ENC28J60-I/SP: Industrial temperature, SPDIP package. b) ENC28J60-I/SO: Industrial temperature, SOIC package. c) ENC28J60T-I/SO: Tape and Reel, Industrial temperature, SOIC package ...
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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2008 Microchip Technology Inc. . EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...