ETC5054N/H STMicroelectronics, ETC5054N/H Datasheet - Page 3

• Manufacturer Part Number: ETC5054N/H
• Description: IC CODEC/FILTER SERIAL 16-DIP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of ETC5054N/H

• Data Interface: Serial
• Resolution (bits): 8 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1339-5

PIN DESCRIPTION
(*) I: Input, O: Output, S: Power Supply
(**) Pins 4,10,11 and 13 are not connected
TRI-STATE® is a trademark of National Semiconductor Corp.
BCLK
MCLK
MCLK
BCLK
GNDA
Name
VF
VF
VF
R
GS
V
FS
FS
TS
V
D
D
/CLKSEL
CC
BB
R
R
X
X
R
X
R
X
X
/PDN
X
O
I
I
–
+
X
X
Type
GND
Pin
O
O
O
O
S
S
*
I
I
I
I
I
I
I
I
I
DIP
and
SO
N
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PLCC
(**)
N
12
14
15
16
17
18
19
20
1
2
3
5
6
7
9
8
Transmit Master Clock
Non-inverting Amplifier
Receive Master Clock
Transmit Time Slot
Inverting Amplifier
Transmit Frame
Analog Ground
Receive Frame
Positive Power
Shift-out Clock
Power Supply
Receive Filter
Receive Data
Shift-in Clock
Data Output
Sync Pulse
Sync Pulse
Function
Negative
Transmit
Gain Set
Supply
Output
Input
Input
Input
V
All signals are referenced to this pin.
Analog Output of the Receive Filter
V
Enables BCLK
8kHz pulse train. See figures 1, 2 and 3 for timing
details.
PCM data is shifted into D
edge.
Shifts data into D
vary from 64 kHz to 2.048 MHz. Alternatively, may be
a logic input which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in synchronous
mode and BCLK
directions (see table 1). This input has an internal pull-
up.
Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous
synchronous with MCLK
MCLK
selected for all internal timing. When MCLK
connected continuously high, the device is powered
down.
Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
Shifts out the PCM data on DX. May vary from 64 kHz
to 2.048 MHz, but must be synchronous with MCLK
The TRI-STATE
by FS
Enables BCLK
an 8 kHz pulse train. See figures 1, 2 and 3 for timing
details.
Open drain output which pulses low during the encoder
time slot. Recommended to be grounded if not used.
Analog output of the transmit input amplifier. Used to
set gain externally.
Inverting Input of the Transmit Input Amplifier.
Non-inverting Input of the Transmit Input Amplifier.
BB
CC
= – 5 V
= + 5 V
X
R
.
is connected continuously low,
5 %.
5 %.
X
R
to shift out the PCM data on D
X
to shift PCM data into D
with
is used for both transmit and receive
R
PCM data output which is enabled
after the FS
Description
MCLK
X
R
for best performance. When
.
R
ETC5054 - ETC5057
following the FS
X
,
R
leading edge. May
but
R
. FS
should
MCLK
R
X
. FS
leading
R
is an
R
X
3/18
X
X
be
.
is
is
is