ADV601JS12 Analog Devices Inc, ADV601JS12 Datasheet - Page 49

• Manufacturer Part Number: ADV601JS12
• Description: IC CODEC VIDEO DSP/SRL 160-MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV601JS12

• Rohs Status: RoHS non-compliant
• Data Interface: DSP, Serial
• Resolution (bits): 10 b
• Sigma Delta: No
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

DSP Interface Timing
The diagram in this section shows transfer timing for one set of video statistics and calculated bin widths as they pass through the
ADV601’s DSP interface. Whenever an ADV601’s serial port is inactive, the codec’s TXD pin is three-stated and the codec ignores
the state of the RXD pin. Figure 41 illustrates the ADV601 serial interface’s signal, sample and frame relationships for the transmit
and receive modes.
Parameter
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
REV. 0
Maximum t
Minimum t
TCLK_DIRQ_D
TCLK_DIRQ_OH
VCLK_TCLK_D
TCLK_TF_D
TCLK_TF_OH
TCLK_TXD_D
TCLK_TXD_OH
TCLK_RF_S
TCLK_RF_H
TCLK_RXD_S
TCLK_RXD_H
(O) TCLK
(O) DIRQ
(I) VCLK
(O) TXD
(I) RXD
(O) TF
(I) RF
TCLK_RXD_H
TCLK_TXD_D
t
TCLK_TF_D
t
TCLK_TXD_OH
t
TCLK_TXD_D
varies with VCLK according to the formula: t
varies with VCLK according to the formula: t
Description
DIRQ Signal, Transfer-Receive Cycle Start, Delay
DIRQ Signal, Transfer-Receive Cycle End, Output Hold
TCLK Signal, Referenced to VCLK, Delay
TF Signal, Transfer Frame Reference to TCLK, Delay
TF Signal, Transfer Frame Reference to TCLK, Output Hold
TXD Sample, Transfer Data, Delay (at 27 MHz VCLK)
TXD Sample, Transfer Data, Output Hold
RF Signal, Receive Frame Referenced to TCLK, Setup
RF Signal, Receive Frame Referenced to TCLK, Hold
RXD Sample, Receive Data, Setup
RXD Sample, Receive Data, Hold (at 27 MHz VCLK)
t
TCLK_DIRQ_D
t
VCLK_TCLK_D
TCLK PERIOD = 4
FIFTY-TWO 16-BIT WORDS TRANSFERRED BY THE ADV601
t
-- ADV601 REGISTERS 0x06 AND 0x80 THROUGH 0xB2
TCLK_TF_OH
Table XXXVII. DSP Read and Write Transfer Timing Parameters
Figure 41. DSP Read and Write Transfer Timing
·
DSP CALCULATES BIN WIDTHS
VCLK PERIOD
FROM VIDEO STATISTICS
TCLK_RXD_H (MIN)
TCLK_TXD_D (MAX)
t
TCLK_RF_S
–49–
= 1.5 (VCLK Period) –36.
= 0.5 (VCLK Period) +4.7.
t
TCLK_RXD_S
t
TCLK_RXD_H
t
TCLK_RF_H
EIGHTY-FOUR 16-BIT WORDS TRANSFERRED BY THE DSP
-- ADV601 REGISTERS 0x100 THROUGH 0x153
t
TCLK_DIRQ_OH
Min
N/A
3
N/A
N/A
2
N/A
2
2
105
2
16.8
2
ADV601
Max
4
N/A
11
3
N/A
24.2
N/A
N/A
N/A
N/A
N/A
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns