ADV601JS12 Analog Devices Inc, ADV601JS12 Datasheet - Page 37

• Manufacturer Part Number: ADV601JS12
• Description: IC CODEC VIDEO DSP/SRL 160-MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV601JS12

• Rohs Status: RoHS non-compliant
• Data Interface: DSP, Serial
• Resolution (bits): 10 b
• Sigma Delta: No
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

TEST CONDITIONS
Figure 23 shows test condition voltage reference and device
loading information. These test conditions consider an output
as disabled when the output stops driving and goes from the
measured high or low voltage to a high impedance state. Tests
measure output disable time (t
reference input signal crossing +1.5 V and the time that the
REV. 0
TIMING PARAMETERS
This section contains signal timing information for the ADV601. Timing descriptions for the following items appear in this
section:
• Clock signal timing
• Video data transfer timing (CCIR-656, Gray Scale/Philips, and Multiplexed Philips formats)
• Host data transfer timing (direct register read/write access)
• DSP data transfer (serial data transfer)
Clock Signal Timing
The diagram in this section shows timing for VCLK input and VCLKO output. All output values assume a maximum pin
loading of 50 pF.
Video Format
CCIR-601 PAL
Square Pixel PAL
CCIR-601 NTSC
Square Pixel NTSC
NOTES
1
2
VCLK Duty Cycle
NOTE
1
Parameter
t
t
t
VCLK Period Drift = 0.1 (VCLK_CYC/field.
VCLK edge-to-edge jitter = 1 ns.
VCLK Duty Cyle = t
VCLK_CYC
VCLKO_D0
VCLKO_D1
REFERENCE
OUTPUT
SIGNAL
SIGNAL
INPUT
VCLK_HI
Description
VCLK Signal, Cycle Time (1/Frequency) at 27 MHz
VCLKO Signal, Delay (when VCLK2 = 0) at 27 MHz
VCLKO Signal, Delay (when VCLK2 = 1) at 27 MHz
V
V
V
V
1
IH
IL
OH
OL
/(t
INPUT & OUTPUT VOLTAGE/TIMING REFERENCES
VCLK_LO
DISABLE
Figure 23. Test Condition Voltage Reference and Device Loading
)
Table XX. Video Clock Period, Frequency, Drift and Jitter
100.
32.2 ns
38.7 ns
Min VCLK_CYC
Period
35.2 ns
35.2 ns
1.5V
) as the time between the
t
DISABLED
Table XXII. Video Clock Timing Parameters
Table XXI. Video Clock Duty Cycle
Min
(40%)
1.5V
–37–
Nominal VCLK_CYC
Period (Frequency)
37 ns (27 MHz)
33.89 ns (29.5 MHz)
37 ns (27 MHz)
40.75 ns (24.54 MHz)
output reaches the high impedance state (also +1.5 V). Simi-
larly, these tests conditions consider an output as enabled when
the output leaves the high impedance state and begins driving a
measured high or low voltage. Tests measure output enable time
(t
+1.5 V and the time that the output reaches the measured high
or low voltage.
ENABLE
t
ENABLED
) as the time between the reference input signal crossing
Nominal
(50%)
Min
(See Video Clock Period Table)
10
10
OUTPUT
DEVICE LOADING FOR AC MEASUREMENTS
PIN
TO
2pF
Max VCLK_CYC
38.9 ns
35.5 ns
38.9 ns
42.7 ns
Max
29
29
Period
I
I
OL
OH
ADV601
1, 2
Max
(60%)
+1.5V
Unit
ns
ns