EMC6D102-CZC SMSC, EMC6D102-CZC Datasheet - Page 63

• Manufacturer Part Number: EMC6D102-CZC
• Description: Industrial Temperature Sensors Auto Fan Contrllr Up to 4 Fans
• Manufacturer: SMSC

Specifications of EMC6D102-CZC

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
7.2.19
Register
Address
64h
65h
66h
RRX-[2:0]
000
001
010
100
101
011
110
111
Read/
Write
R/W
R/W
R/W
Description of Ramp Rate Control bits:
If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature
spikes may be sampled by the part. The auto fan control logic calculates the PWM duty cycle for all
temperature readings. If Ramp Rate Control is disabled, the PWM output will jump or oscillate
between different PWM duty cycles causing the fan to suddenly change speeds, which creates
unwanted fan noise. If enabled, the PWM Ramp Rate Control logic will prevent the PWM output from
jumping, instead the PWM will ramp up/down towards the new duty cycle at a pre-determined ramp
rate.
Ramp Rate Control
The Ramp Rate Control logic limits the amount of change to the PWM duty cycle over a period of time.
This period of time is programmable via the Ramp Rate Control bits. For a detailed description of the
Ramp Rate Control bits see
Rate Control Logic on page
Note:
Registers 64-66h: Minimum PWM Duty Cycle
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
RR1E, RR2E, and RR3E enable PWM Ramp Rate Control for PWM 1, 2, and 3 respectively.
RR1-2, RR1-1, and RR1-0 control ramp rate time for PWM 1
RR2-2, RR2-1, and RR2-0 control ramp rate time for PWM 2
RR3-2, RR3-1, and RR3-0 control ramp rate time for PWM 3
100% DUTY CYCLE)
PWM RAMP TIME
(TIME FROM 33%
DUTY CYCLE TO
PWM1 Minimum Duty Cycle
PWM2 Minimum Duty Cycle
PWM3 Minimum Duty Cycle
(SEC)
Register Name
17.6
11.8
7.0
4.4
3.0
1.6
0.8
35
Table 7.12 PWM Ramp Rate Control
34.
Table
100% DUTY CYCLE)
7.12. For a description of the Ramp Rate Control logic see
PWM RAMP TIME
DATASHEET
DUTY CYCLE TO
(TIME FROM 0%
(MSb)
Bit 7
7
7
7
17.595
10.455
(SEC)
52.53
26.52
1.275
6.63
4.59
2.55
63
Bit 6
6
6
6
Bit 5
5
5
5
TIME PER PWM STEP
Bit 4
(PWM STEP SIZE =
4
4
4
206 msec
104 msec
Bit 3
69 msec
41 msec
26 msec
18 msec
10 msec
5 msec
3
3
3
1/255)
Bit 2
2
2
2
Bit 1
Revision 0.4 (09-25-07)
1
1
1
RAMP RATE
(LSb)
Bit 0
0
0
0
PWM
14.49
24.39
38.46
55.56
4.85
9.62
(HZ)
100
200
Default
Value
Ramp
80h
80h
80h