STTS424E02CDA6F STMicroelectronics, STTS424E02CDA6F Datasheet - Page 30

• Manufacturer Part Number: STTS424E02CDA6F
• Description: Board Mount Temperature Sensors MEM Module Temp Sens 2Kb SPD
• Manufacturer: STMicroelectronics

Specifications of STTS424E02CDA6F

• Full Temp Accuracy: +/- 3 C
• Package / Case: DFN EP
• Digital Output - Bus Interface: Serial (2-Wire, I2C)
• Digital Output - Number Of Bits: 10 bit
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Output Type: Analog
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SPD EEPROM operation
5.4.1
5.4.2
5.5
30/50
SWP and CWP
If the software write-protection has been set with the SWP instruction, it can be cleared
again with a CWP instruction.
The two instructions (SWP and CWP) have the same format as a byte write instruction, but
with a different device type identifier (as shown in
is followed by an address byte and a data byte, but in this case the contents are all “Don’t
Care”
and specific logical levels must be applied on the other two address pins A1 and A2 (as
shown in
PSWP
If the software write-protection has been set with the PSWP instruction, the first 128 bytes of
the memory are permanently write-protected. This write-protection cannot be cleared by any
instruction, or by power-cycling the device. Also, once the PSWP instruction has been
successfully executed, the SPD EEPROM no longer acknowledges any instruction (with a
device type identifier of 0110) to access the write-protection settings.
Figure 11. Setting the write protection
Write operations
Following a start condition the bus master sends a device select code with the R/W bit reset
to 0. The device acknowledges this, as shown in
The device responds to the address byte with an acknowledge bit, and then waits for the
data byte.
When the bus master generates a stop condition immediately after the ACK bit (in the “10
bit” time slot), either at the end of a byte write or a page write, the internal memory write
cycle is triggered. A stop condition at any other time slot does not trigger the internal write
cycle.
During the internal write cycle, serial data (SDA) and serial clock (SCL) are ignored, and the
device does not respond to any requests.
(Figure
Table
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
11). Another difference is that the voltage, V
20).
Doc ID 13448 Rev 8
CONTROL
BYTE
ACK
(DON'T CARE)
ADDRESS
WORD
VALUE
Figure
Table
ACK
20). Like the byte write instruction, it
12, and waits for an address byte.
(DON'T CARE)
HV
, must be applied on the A0 pin,
VALUE
DATA
ACK
STTS424E02
AI01935b
th