EMC1402-4-ACZL-TR SMSC, EMC1402-4-ACZL-TR Datasheet - Page 17

• Manufacturer Part Number: EMC1402-4-ACZL-TR
• Description: Board Mount Temperature Sensors Dual Temp Snsr
• Manufacturer: SMSC

Specifications of EMC1402-4-ACZL-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1°C Temperature Sensor with Beta Compensation
Datasheet
SMSC EMC1402
5.3
5.3.1
5.3.2
5.4
5.5
When the THERM pin is asserted, the Therm status bits will likewise be set. Reading these bits will
not clear them until the THERM pin is deasserted. Once the THERM pin is deasserted, the THERM
status bits will be automatically cleared.
The ALERT pin is an open drain output and requires a pull-up resistor to V
operation: interrupt mode and comparator Mode. The mode of the ALERT output is selected via the
ALERT / COMP bit in the Configuration Register (see
ALERT Pin Interrupt Mode
When configured to operate in interrupt mode, the ALERT pin asserts low when an out of limit
measurement (> high limit or < low limit) is detected on any diode or when a diode fault is detected.
The ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit
condition has been removed, the ALERT pin will remain asserted until the appropriate status bits are
cleared.
The ALERT pin can be masked by setting the MASK bit. Once the ALERT pin has been masked, it
will be de-asserted and remain de-asserted until the MASK bit is cleared by the user. Any interrupt
conditions that occur while the ALERT pin is masked will update the Status Register normally.
The ALERT pin is used as an interrupt signal or as an Smbus Alert signal that allows an SMBus slave
to communicate an error condition to the master. One or more ALERT outputs can be hard-wired
together.
ALERT Pin Comparator Mode
When the ALERT pin is configured to operate in comparator mode it will be asserted if any of the
measured temperatures exceeds the respective high limit. The ALERT pin will remain asserted until
all temperatures drop below the corresponding high limit minus the THERM Hysteresis value.
When the ALERT pin is asserted in comparator mode, the corresponding high limit status bits will be
set. Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is
deasserted, the status bits will be automatically cleared.
The MASK bit will not block the ALERT pin in this mode, however the individual channel masks (see
Section
The EMC1402 is configured to monitor the temperature of basic diodes (e.g. 2N3904), or CPU thermal
diodes. It automatically detects the type of external diode (CPU diode or diode connected transistor)
and determines the optimal setting to reduce temperature errors introduced by beta
variation.Compensating for this error is also known as implementing the transistor or BJT model for
temperature measurement.
For discrete transistors configured with the collector and base shorted together, the beta is generally
sufficiently high such that the percent change in beta variation is very small. For example, a 10%
variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute
approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction
is used for temperature measurement and the collector is tied to the substrate, the proportional beta
variation will cause large error. For example, a 10% variation in beta for two forced emitter currents
with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C.
Parasitic resistance in series with the external diodes will limit the accuracy obtainable from
temperature measurement devices. The voltage developed across this resistance by the switching
diode currents cause the temperature measurement to read higher than the true temperature.
Contributors to series resistance are PCB trace resistance, on die (i.e. on the processor) metal
resistance, bulk resistance in the base and emitter of the temperature transistor. Typically, the error
ALERT Output
Beta Compensation
Resistance Error Correction (REC)
6.10) will prevent the respective channel from asserting the ALERT pin.
DATASHEET
17
Section
6.4).
DD
and has two modes of
Revision 1.36 (07-02-09)