EMC1423-1-AIZL-TR SMSC, EMC1423-1-AIZL-TR Datasheet - Page 37

• Manufacturer Part Number: EMC1423-1-AIZL-TR
• Description: Board Mount Temperature Sensors TRIPLE TEMP SNSR
• Manufacturer: SMSC

Specifications of EMC1423-1-AIZL-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1°C Temperature Sensor with Hardware Thermal Shutdown
Datasheet
SMSC EMC1423/EMC1424
6.11
6.12
ADDR.
1Fh
ADDR.
1Eh
R/W
R/W
R/W
R
Bit 1 - E1SYS - configures the External Diode 1 channel to assert the SYS_SHDN pin based on the
THERM Limit.
Bit 0 - INTSYS - configures the Internal Diode channel to assert the SYS_SHDN pin based on it’s
respective THERM Limit.
This read only register returns the Hardware Thermal Shutdown Limit selected by the value of the pull-
up resistors on the ALERT and SYS_SHDN pins. The data represents the hardware set temperature
in °C using the active temperature setting set by the RANGE bit in the Configuration Register. See
Table 6.5
When the External Diode 1 Temperature exceeds this limit, the SYS_SHDN pin is asserted and will
remain asserted until the External Diode 1 Temperature drops below this limit minus 10°C.
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads a diode fault or out of limit error. The
channel mask does not mask the SYS_SHDN pin.
Bit 3 - E3MASK - Masks the ALERT pin from asserting when the External Diode 3 channel is out of
limit or reports a diode fault.
Hardware Thermal Shutdown Limit Register
Channel Mask Register
‘0’ (default) - the External Diode 2 channel is not linked to the SYS_SHDN pin. If the temperature
exceeds it’s THERM Limit, the E2THERM status bit is set but the SYS_SHDN pin is not asserted.
‘1’ - the External Diode 2 channel is linked to the SYS_SHDN pin. If the temperature exceeds it’s
THERM Limit, the E2THERM status bit is set and the SYS_SHDN pin is asserted. It will remain
asserted until the temperature drops below it’s THERM Limit minus the THERM Hysteresis.
‘0’ (default) - the External Diode 1 channel is not linked to the SYS_SHDN pin. If the temperature
exceeds the THERM Limit, the E1THERM status bit is set but the SYS_SHDN pin is not asserted.
‘1’ - the External Diode 1 channel is linked to the SYS_SHDN pin. If the temperature exceeds the
THERM Limit, the E1THERM status bit is set and the SYS_SHDN pin is asserted. It will remain
asserted until the temperature drops below the THERM Limit minus the THERM Hysteresis.
‘0’ (default) - the Internal Diode channel is not linked to the SYS_SHDN pin. If the temperature
exceeds it’s THERM Limit, the ITHERM status bit is set but the SYS_SHDN pin is not asserted.
‘1’ - the Internal Diode channel is linked to the SYS_SHDN pin. If the temperature exceeds it’s
THERM Limit, the ITHERM status bit is set and the SYS_SHDN pin is asserted. It will remain
asserted until the temperature drops below it’s THERM Limit minus the THERM Hysteresis.
REGISTER
Channel
Shutdown Limit
Mask
for the data format.
REGISTER
Hardware
Thermal
Table 6.12 Hardware Thermal Shutdown Limit Register
B7
-
Table 6.13 Channel Mask Register
128
B7
B6
-
DATASHEET
B6
64
B5
-
37
B5
32
B4
-
B4
16
MASK
B3
E3
B3
8
MASK
E2
B2
B2
4
MASK
E1
B1
B1
2
Revision 1.36 (07-02-09)
MASK
B0
1
INT
B0
DEFAULT
DEFAULT
N/A
00h