EMC1422-1-ACZL-TR SMSC, EMC1422-1-ACZL-TR Datasheet - Page 33

no-image

EMC1422-1-ACZL-TR

Manufacturer Part Number
EMC1422-1-ACZL-TR
Description
Board Mount Temperature Sensors Dual Temp Snsr
Manufacturer
SMSC
Datasheet

Specifications of EMC1422-1-ACZL-TR

Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EMC1422-1-ACZL-TR
Manufacturer:
NSC
Quantity:
6 974
Part Number:
EMC1422-1-ACZL-TR
Manufacturer:
SMSC
Quantity:
20 000
Company:
Part Number:
EMC1422-1-ACZL-TR
Quantity:
117
ADDR.
35h
ADDR.
1°C Temperature Sensor with Hardware Thermal Shutdown
Datasheet
APPLICATION NOTE: When measuring a 65nm Intel CPUs, the Ideality Setting should be the default 12h. When
SMSC EMC1422
36h
6.14
6.15
R/W
R-C
2
0
0
0
1
R/W
R-C
The High Limit Status Register contains the status bits that are set when a temperature channel high
limit is exceeded. If any of these bits are set, then the HIGH status bit in the Status Register is set.
Reading from the High Limit Status Register will clear all bits if. Reading from the register will also
clear the HIGH status bit in the Status Register.
The ALERT pin will be set if the programmed number of consecutive alert counts have been met and
any of these status bits are set.
The status bits will remain set until read unless the ALERT pin is configured as a comparator output
(see
Bit 1 - EHIGH - This bit is set when the External Diode channel exceeds its programmed high limit.
Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.
The Low Limit Status Register contains the status bits that are set when a temperature channel drops
below the low limit. If any of these bits are set, then the LOW status bit in the Status Register is set.
Reading from the Low Limit Status Register will clear all bits. Reading from the register will also clear
the LOW status bit in the Status Register.
High Limit Status Register
Low Limit Status Register
REGISTER
High Limit
Status
Section
REGISTER
Low Limit
Status
measuring 45nm Intel CPUs, the Ideality Setting should be 15h.
1
0
0
1
1
5.3.2).
B7
-
Table 6.15 Consecutive Alert / THERM Settings
B7
-
Table 6.16 High Limit Status Register
Table 6.17 Low Limit Status Register
B6
-
B6
0
0
1
1
1
-
B5
DATASHEET
-
B5
-
33
B4
-
B4
-
NUMBER OF CONSECUTIVE OUT OF LIMIT
B3
B3
-
-
(default for CTHRM[2:0])
(default for CALRT[2:0])
MEASUREMENTS
B2
B2
-
-
1
2
3
4
ELOW
EHIGH
B1
B1
Revision 1.36 (07-02-09)
ILOW
IHIGH
B0
B0
DEFAULT
DEFAULT
00h
00h

Related parts for EMC1422-1-ACZL-TR