EMC1422-1-ACZL-TR SMSC, EMC1422-1-ACZL-TR Datasheet - Page 31

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EMC1422-1-ACZL-TR

Manufacturer Part Number
EMC1422-1-ACZL-TR
Description
Board Mount Temperature Sensors Dual Temp Snsr
Manufacturer
SMSC
Datasheet

Specifications of EMC1422-1-ACZL-TR

Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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1°C Temperature Sensor with Hardware Thermal Shutdown
Datasheet
SMSC EMC1422
6.11
6.12
ADDR.
6.13
1Fh
ADDR.
ADDR.
1Eh
22h
R/W
R/W
R/W
R/W
R
R/W
This read only register returns the Hardware Thermal Shutdown Limit selected by the value of the pull-
up resistors on the ALERT and SYS_SHDN pins. The data represents the hardware set temperature
in °C using the active temperature setting set by the RANGE bit in the Configuration Register. See
Table 6.5
When the External Diode Temperature exceeds this limit, the SYS_SHDN pin is asserted and will
remain asserted until the External Diode Temperature drops below this limit minus 10°C.
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads a diode fault or out of limit error. The
channel mask does not mask the SYS_SHDN pin.
Bit 1 - EMASK - Masks the ALERT pin from asserting when the External Diode channel is out of limit
or reports a diode fault.
Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out
of limit.
Hardware Thermal Shutdown Limit Register
Channel Mask Register
Consecutive ALERT Register
‘0’ (default) - The External Diode channel will cause the ALERT pin to be asserted if it is out of
limit or reports a diode fault.
‘1’ - The External Diode channel will not cause the ALERT pin to be asserted if it is out of limit or
reports a diode fault.
‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out of limit.
‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out of limit.
REGISTER
Channel
Shutdown Limit
Mask
Consecutive
REGISTER
for the data format.
REGISTER
Hardware
ALERT
Thermal
Table 6.12 Hardware Thermal Shutdown Limit Register
B7
-
Table 6.14 Consecutive ALERT Register
TIME
OUT
Table 6.13 Channel Mask Register
B7
128
B7
B6
-
B6
DATASHEET
B6
64
CTHRM[2:0]
B5
-
B5
31
B5
32
B4
-
B4
B4
16
B3
-
B3
B3
8
CALRT[2:0]
B2
B2
-
B2
4
MASK
B1
B1
E
B1
2
Revision 1.36 (07-02-09)
B0
MASK
-
B0
1
INT
B0
DEFAULT
DEFAULT
DEFAULT
N/A
70h
00h

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