W681360WG Nuvoton Technology Corporation of America, W681360WG Datasheet - Page 8

• Manufacturer Part Number: W681360WG
• Description: IC VOICEBND CODEC 3V 1CH 20TSSOP
• Manufacturer: Nuvoton Technology Corporation of America
• Type: PCMr

Specifications of W681360WG

• Data Interface: PCM Audio Interface
• Resolution (bits): 13 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: 2.7 V ~ 5.25 V
• Voltage - Supply, Digital: 2.7 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: W681360ES - KIT EVAL FOR W681360
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

7. FUNCTIONAL DESCRIPTION
W681360 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC
complies with the specifications of the ITU-T G.712 recommendation.
The CODEC block diagram in Section 3 illustrates the main components of the W681360. The chip
consists of a PCM interface, which can process long and short frame sync formats. The pre-scaler of
the chip provides the internal clock signals and synchronizes the CODEC sample rate with the
external frame sync frequency. The power conditioning block provides the internal power supply for
the digital and the analog section, while the voltage reference block provides a precision analog
ground voltage for the analog signal processing.
The calibration level for both the Analog to Digital Converter (ADC) and the Digital to Analog
Converter (DAC) is referenced to μ-Law with the same bit voltage weighing about the zero crossing,
resulting in the 0dBm0 calibration level 3.2dB below the peak sinusoidal level before clipping, Based
on the reference voltage of 0.886V the calibration level is 0.436 Vrms or –5dBm at 600Ω.
The first stage of the A-to-D path of the CODEC is an analog input operational
amplifier with externally configurable gain settings. A differential analog input may be
applied to the Inputs AI+ and AI-. Alternately the input amplifier may be powered
down and a single-ended input signal can be applied to either the AO pin or the AI-
pin. The input amplifier can be powered down by connecting the AI+ pin to either V
or V
7.1. Transmit Path
SS
DATA
DATA
Receive
Receive
DATA
DATA
Transmit
Transmit
which also determines whether AO or AI+ is selected as input according to
13
13
13
13
13 bit linear
13 bit linear
13 bit linear
13 bit linear
DAC
DAC
ADC
ADC
FIGURE 7.1: THE W681360 SIGNAL PATH
f
f
High Pass
High Pass
C
C
= 200 Hz
= 200 Hz
Filter
Filter
High Pass
High Pass
Bypass
Bypass
- 8 -
f
f
f
f
Anti-Aliasing
Anti-Aliasing
C
C
C
C
Smoothing
Smoothing
= 3400 Hz
= 3400 Hz
= 3400 Hz
= 3400 Hz
Filter a
Filter a
Filter a
Filter a
Publication Release Date: September 2005
Anti-Aliasing
Anti-Aliasing
Smoothing
Smoothing
Filter b
Filter b
Filter b
Filter b
VAG
VAG
Buffer1
Buffer1
Av=1
Av=1
-
-
+
+
+
+
-
-
W681360
-
-
+
+
Revision A.2
PAO+
PAO+
PAO-
PAO-
AI-
AI-
AI-
AI+
AI+
AI+
PAI
PAI
AO
AO
RO-
RO-
DD