CS42516-DQZR Cirrus Logic Inc, CS42516-DQZR Datasheet - Page 64

• Manufacturer Part Number: CS42516-DQZR
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42516-DQZR

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 110
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC, 6 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1502 - BOARD EVAL FOR CS42518 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

64
6.20.1 PLL UNLOCK (UNLOCK)
6.20.2 NEW Q-SUBCODE BLOCK (QCH)
6.20.3 D TO E C-BUFFER TRANSFER (DETC)
6.20.4 D TO E U-BUFFER TRANSFER (DETU)
6.20.5 ADC OVERFLOW (OVERFLOW)
6.20.6 RECEIVER ERROR (RERR)
6.21
UNLOCKM
7
Interrupt Mask (address 21h)
Default = 0
Function:
PLL unlock status bit. This bit will go high if the PLL becomes unlocked.
Default = 0
Function:
Indicates when the Q-Subcode block has changed.
Default = 0
Function:
Indicates when the channel status buffer has changed.
Default = 0
Function:
Indicates when the user status buffer has changed.
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS42516 ADC signal path.
Default = 0
Function:
Indicates that a receiver error has occurred. The register
on page 67
Default = 00000000
Function:
The bits of this register serve as a mask for the interrupt sources found in the register
(address 20h) (Read Only)” on page
its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is
masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions
align with the corresponding bits in the Interrupt Status register.
Reserved
6
may be read to determine the nature of the error which caused the interrupt.
QCHM
5
DETCM
4
63. If a mask bit is set to 1, the error is unmasked, meaning that
DETUM
3
“Receiver Errors (address 26h) (Read Only)”
Reserved
2
OverFlowM
1
“Interrupt Status
CS42516
RERRM
DS583F1
0