LM4550BVH/NOPB National Semiconductor, LM4550BVH/NOPB Datasheet - Page 18

• Manufacturer Part Number: LM4550BVH/NOPB
• Description: IC AC '97 AUDIO CODEC 48-LQFP
• Manufacturer: National Semiconductor
• Type: Audio Codec '97r

Specifications of LM4550BVH/NOPB

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 89
• Voltage - Supply, Analog: 4.2 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 3
• Adc / Dac Resolution: 18bit
• Sampling Rate: 48kSPS
• Interface Type: Serial
• Supply Voltage Range: 3V To 5.5V, 4.2V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM4550BVH; *LM4550BVH/NOPB; LM4550BVH

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Functional Description
REGISTER RESET is performed when any value is written
to the RESET register, 00h. It resets all registers to their
AC Link Serial Interface Protocol
AC LINK OUTPUT FRAME:
SDATA_OUT, CONTROLLER OUTPUT TO LM4550B INPUT
The AC Link Output Frame carries control and PCM data to
the LM4550B control registers and stereo DAC. Output
Frames are carried on the SDATA_OUT signal which is an
output from the AC ’97 Digital Controller and an input to the
LM4550B codec. As shown in Figure 3, Output Frames are
constructed from thirteen time slots: one Tag Slot followed by
twelve Data Slots. Each Frame consists of 256 bits with each
of the twelve Data Slots containing 20 bits. Input and Output
Frames are aligned to the same SYNC transition. Note that
the LM4550B only accepts data in eight of the twelve Data
Slots and, since it is a two channel codec only in 4 simulta-
neously – 2 for control, one each for PCM data to the left and
right channel DACs. Data-Slot to DAC mappings are tied to
the codec mode selected by the Identity pins ID1#, ID0# and
are given in Table 1.
FIGURE 3. AC Link Bidirectional Audio Frame
(Continued)
FIGURE 4. AC Link Output Frame
18
default state and will modify circuit configurations accord-
ingly but does not reset any other internal circuits.
A new Output Frame is signaled with a low-to-high transition
of SYNC. SYNC should be clocked from the controller on a
rising edge of BIT_CLK and, as shown in Figure 4 and
Figure 5, the first tag bit in the Frame (“Valid Frame”) should
be clocked from the controller by the next rising edge of
BIT_CLK and sampled by the LM4550B on the following
falling edge. The AC ’97 Controller should always clock data
to SDATA_OUT on a rising edge of BIT_CLK and the
LM4550B always samples SDATA_OUT on the next falling
edge. SYNC is sampled with the falling edge of BIT_CLK.
The LM4550B checks each Frame to ensure 256 bits are
received. If a new Frame is detected (a low-to-high transition
on SYNC) before 256 bits are received from the old Frame
then the new Frame is ignored i.e. the data on SDATA_OUT
is discarded until a valid new Frame is detected.
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