CS42448-DQZ Cirrus Logic Inc, CS42448-DQZ Datasheet - Page 33

• Manufacturer Part Number: CS42448-DQZ
• Description: IC CODEC 108DB 192KHZ 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42448-DQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 6 ADC, 8 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1151 - BOARD EVAL FOR CS42448 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1615

DS648F3
4.5.5
4.5.6
ADC/DAC_LRCK
ADC/DAC_SCLK
ADC_SDOUT1
DAC_SDIN1
ADC/DAC_LRCK
ADC/DAC_SCLK
ADC_SDOUT1
OLM #2
OLM #2 serial audio interface format operates in Single- or Double-Speed Mode and will master or slave
ADC/DAC_SCLK at 256Fs.
TDM
TDM data is received most significant bit (MSB) first, on the second rising edge of the DAC_SCLK occur-
ring after a DAC_LRCK rising edge. All data is valid on the rising edge of DAC_SCLK. The AIN1 MSB is
transmitted early, but is guaranteed valid for a specified time after SCLK rises. All other bits are transmit-
ted on the falling edge of ADC_SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘jus-
tified within the time slot. Valid data lengths are 16, 18, 20, or 24.
ADC/DAC_SCLK must operate at 256Fs. ADC/DAC_LRCK identifies the start of a new frame and is equal
to the sample rate, Fs.
ADC/DAC_LRCK is sampled as valid on the rising ADC/DAC_SCLK edge preceding the most significant
bit of the first data sample and must be held valid for at least 1 ADC/DAC_SCLK period.
Note:
DAC_SDIN1
DAC_SDIN4
LSB
MSB
MSB
The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode.
32 clks
32 clks
AOUT1
AIN1
MSB
AOUT1
AOUT7
AIN1
24 clks
24 clks
24 clks
LSB
LSB
Bit or Word Wide
MSB
MSB
LSB
32 clks
32 clks
AOUT2
AIN2
MSB
AOUT3
Figure 19. One Line Mode #2 Format
AIN3
Left Channel
24 clks
24 clks
LSB
LSB
128 clks
MSB
MSB
LSB
Figure 20. TDM Format
AOUT3
32 clks
32 clks
AIN3
MSB
AOUT5
24 clks
AIN5
24 clks
LSB
LSB
MSB
MSB
LSB
32 clks
32 clks
AOUT4
AIN4
LSB
LSB
256 clks
MSB
MSB
MSB
AOUT8
24 clks
24 clks
AIN2
24 clks
AOUT2
AOUT5
32 clks
32 clks
AIN5
LSB
LSB
LSB
MSB
MSB
MSB
Right Channel
AOUT4
AIN4
24 clks
24 clks
128 clks
AOUT6
32 clks
32 clks
AIN6
LSB
LSB
LSB
MSB
MSB
MSB
AOUT6
24 clks
AIN6
24 clks
AOUT7
32 clks
32 clks
AUX1
LSB
LSB
LSB
MSB
MSB
MSB
CS42448
AOUT8
32 clks
32 clks
AUX2
LSB
LSB
MSB
MSB
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