CS42518-CQZ Cirrus Logic Inc, CS42518-CQZ Datasheet - Page 69

• Manufacturer Part Number: CS42518-CQZ
• Description: IC CODEC S/PDIF RCVR 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: General Purposer

Specifications of CS42518-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 110
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/8 DAC
• Thd Plus Noise: - 100 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1502 - BOARD EVAL FOR CS42518 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1036

DS584F1
6.27
6.27.1 MUTEC POLARITY SELECT (MCPOLARITY)
6.27.2 CHANNEL MUTES SELECT (M_AOUTXX)
6.28
6.28.1 MODE CONTROL (MODEX)
Reserved
Mode1
7
7
Mutec Pin Control (address 28h)
RXP/General-Purpose Pin Control (addresses 29h to 2Fh)
the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence
will not appear in the receiver error register, will not affect the RERR interrupt, and will not affect the
current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not
affect the current audio sample even when unmasked.
Default = 0
0 - Active low
1 - Active high
Function:
Determines the polarity of the MUTEC pin.
Default = 11111
0 - Channel mute is not mapped to the MUTEC pin
1 - Channel mute is mapped to the MUTEC pin
Function:
Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are
mapped, then the MUTEC pin is driven to the “active” state as defined by the POLARITY bit. These
Channel Mute Select bits are “ANDed” together in order for the MUTEC pin to go active. This means
that if multiple Channel Mutes are selected to be mapped to the MUTEC pin, all corresponding chan-
nels must be muted before the MUTEC will go active.
Default = 00
00 - RXP Input
01 - Mute Mode
10 - GPO/Overflow Mode
11 - GPO, Drive High Mode
Function:
RXP Input - The pin is configured as a receiver input which can then be muxed to either the TXP pin
or to the internal receiver.
Mute Mode - The pin is configured as a dedicated mute pin. The muting function is controlled by the
Function bits.
GPO, Drive Low / ADC Overflow Mode - The pin is configured as a general-purpose output driven low
Reserved
Mode0
6
6
MCPolarity
Polarity
5
5
M_AOUTA1
Function4
4
4
M_AOUTB1
Function3
3
3
M_AOUTA2
M_AOUTB2
Function2
2
2
M_AOUTA3
M_AOUTB3
Function1
1
1
CS42518
M_AOUTB4
M_AOUTA4
Function0
0
0
69