CS42418-CQZ Cirrus Logic Inc, CS42418-CQZ Datasheet - Page 25
![IC CODEC 8CH PLL 192KHZ 64LQFP](/photos/6/80/68060/cs42418-cqz_sml.jpg)
CS42418-CQZ
Manufacturer Part Number
CS42418-CQZ
Description
IC CODEC 8CH PLL 192KHZ 64LQFP
Manufacturer
Cirrus Logic Inc
Type
General Purposer
Datasheet
1.CS42418-CQZ.pdf
(73 pages)
Specifications of CS42418-CQZ
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 110
Voltage - Supply, Analog
4.75 V ~ 5 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
15
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
110dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1029
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DS603F1
4.5
4.5.1
OMCK/LRCK Ratio
SCLK/LRCK Ratio
Digital Interfaces
When the device is clocked from OMCK, the frequency of OMCK must be at least twice the frequency of
the fastest Slave Mode, SCLK. For example, if both serial ports are in Slave Mode with one SCLK running
at 32x Fs and the other at 64x Fs, the slowest OMCK signal that can be used to clock the device is
128x Fs.
When either serial port is in Slave Mode, its respective LRCK signal must be present for proper device
operation.
In Slave Mode, One-Line Mode #1 is supported; One-Line Mode #2 is not.
The sample rate to OMCK ratios and OMCK frequency requirements for Slave Mode operation are shown
in
Serial Audio Interface Signals
The CS42418 interfaces to an external Digital Audio Processor via two independent serial ports, the
DAC serial port, DAC_SP, and the ADC serial port, ADC_SP. The digital output of the internal ADCs use
the ADC_SDOUT pin and can be configured to use either the ADC or DAC serial port timings.These con-
figuration bits and the selection of Single-, Double- or Quad-Speed Mode for DAC_SP and ADC_SP are
found in register
The serial interface clocks, ADC_SCLK for ADC_SP and DAC_SCLK for DAC_SP, are used for transmit-
ting and receiving audio data. Either ADC_SCLK or DAC_SCLK can be generated by the CS42418 (Mas-
ter Mode), or it can be input from an external source (Slave Mode). Master or Slave Mode selection is
made using bits DAC_SP M/S and ADC_SP M/S in register
The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the
start of a new sample period. It may be an output of the CS42418 (Master Mode), or it may be generated
by an external source (Slave Mode). As described in later sections, particular modes of operation do allow
the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other.
The serial data interface format selection (Left/Right-Justified, I²S or One-Line Mode) for the ADC serial
port data out pin, ADC_SDOUT, and the DAC input pins, DAC_SDIN1:4, is configured using the appro-
priate bits in the register
in two's complement binary form with the MSB first in all formats.
DAC_SDIN1, DAC_SDIN2, DAC_SDIN3and DAC_SDIN4 are the serial data input pins supplying the in-
ternal DAC. ADC_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs and,
when configured for one-line mode, up to four additional ADC channels attached externally to the signals
ADCIN1 and ADCIN2 (typically two CS5361 stereo ADCs). When operated in One-Line Mode, 6 channels
of DAC data are input on DAC_SDIN1, two additional DAC channels on DAC_SDIN4, and 6 channels of
ADC data are output on ADC_SDOUT.
Table
1. Refer to
“Functional Mode (address 03h)” on page
Table 3
32x, 48x, 64x, 128x
256x, 384x, 512x
Single-Speed
“Interface Formats (address 04h)” on page
for required clock ratios.
Table 3. Slave Mode Clock Ratios
Table 4 on page 26
128x, 192x, 256x
Double-Speed
32x, 48x, 64x
43.
outlines the serial port channel allocations.
“Misc Control (address 05h)” on page
Quad-Speed
64x, 96x, 128x
32x, 48x, 64x
45. The serial audio data is presented
One-Line Mode #1
CS42418
256x
128x
46.
25