CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 46

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

8.2
The
(Index 26h) controls the power management func-
tions. The PR[6:0] bits in this register control the
internal powerdown states of the CS4202. Power-
down control is available for individual subsections
of the CS4202 by asserting any PRx bit or any com-
bination of PRx bits. All powerdown states except
PR4 and PR5 can be resumed by clearing the cor-
responding PRx bit. Table 15 shows the mapping
of the power control bits to the functions they man-
age.
When PR0 is ‘set’, the L/R ADCs and the Input
Mux are shut down and the ADC bit in the Power-
down Control/Status Register (Index 26h) is
‘cleared’ indicating the ADCs are no longer in a
ready state. The same is true for PR1 and the
DACs, PR2 and the analog mixer, PR3 and the
voltage reference (Vrefout), and PR6 and the head-
phone amplifier. When one of these bits is
‘cleared’, the corresponding subsystem will begin a
power-on process, and the associated status bit will
be ‘set’ when the hardware is ready.
In a primary codec the PR4 bit powers down the
AC-link, but all other analog and digital sub-
46
Powerdown Controls
Powerdown
Control/Status
* Applies only to primary codec
PR Bit
PR0
PR1
PR2
PR3
PR4
PR5
PR6
Table 15. Powerdown PR Bit Functions
L/R ADCs and Input Mux Powerdown
Register
Analog Mixer Powerdown (Vref on)
Analog Mixer Powerdown (Vref off)
AC-link Powerdown (BIT_CLK off)*
Headphone Out Powerdown
Front DACs Powerdown
Internal Clock Disable
Function
systems continue to function. The required resume
sequence from a PR4 state is either a Warm Reset
or a New Warm Reset, depending on whether a
D3
The PR5 bit disables all internal clocks and powers
down the DACs and the ADCs, but maintains oper-
ation of the BIT_CLK and the analog mixer. A
Cold Reset is the only way to restore operation to
the CS4202 after asserting PR5. To achieve a com-
plete digital powerdown, PR4 and PR5 must be as-
serted within a single AC output frame. This will
also drive BIT_CLK ‘low’.
The CS4202 does not automatically mute any input
or output when the powerdown bits are ‘set’. The
software driver controlling the AC ’97 device must
manage muting the input and output analog signals
before putting the part into any power management
state. The definition of each PRx bit may affect a
single subsection or a combination of subsections
within the CS4202. Table 16 contains the matrix of
subsections affected by the respective PRx func-
tion. Table 17 shows the different operating power
consumptions levels for different powerdown func-
tions.
hot
or D3
cold
state has been entered.
CS4202
DS549PP2