CS42L52-CNZ Cirrus Logic Inc, CS42L52-CNZ Datasheet - Page 22

• Manufacturer Part Number: CS42L52-CNZ
• Description: IC CODEC STER HDPN & SPKR 40QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L52-CNZ

• Package / Case: 40-QFN
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 99 / 98
• Voltage - Supply, Analog: 1.65 V ~ 2.63 V
• Voltage - Supply, Digital: 1.65 V ~ 2.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2C)
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 88 dB ADC / - 86 dB DAC
• Package: 40QFN EP
• Adc/dac Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Number Of Dacs: 2
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1580 - REFERENCE DESIGN FOR CS42L52598-1508 - BOARD EVAL FOR 42LDB1 CODEC598-1505 - BOARD EVAL FOR CS42L52 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1628

22
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDA C
SCL Clock Frequency
RESET
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
16. Data must be held for sufficient time to bridge the transition time, t
Rising Edge to Start
RST
SDA
SCL
Stop
t irs
t buf
Parameters
Start
t hdst
t
low
Figure 4. Control Port Timing - I²C
L
t
= 30 pF.
hdd
t high
(Note 16)
5/13/08
t sud
Symbol
t
t
t
t
t
t
Repeated
t
susp
t
t
f
hdst
high
sust
t
hdd
sud
low
t
t
ack
buf
scl
t sust
irs
rc
fc
Start
t
hdst
fc
, of SCL.
Min
550
250
300
4.7
4.0
4.7
4.0
4.7
4.7
t r
0
-
-
-
t f
Max
1000
100
300
1
-
-
-
-
-
-
-
-
-
Stop
t susp
CS42L52
DS680F1
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns