CY7C342B-15JC Cypress Semiconductor Corp, CY7C342B-15JC Datasheet - Page 7

• Manufacturer Part Number: CY7C342B-15JC
• Description: IC EPLD 128MACROCELL 15NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C342B-15JC

• Programmable Type: EPLD
• Number Of Macrocells: 128
• Voltage - Input: 5V
• Speed: 15ns
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: MAX®
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 52
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Memory Type: EPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1262

Commercial and Industrial External Asynchronous Switching Characteristics
Commercial and Industrial Typical Internal Switching Characteristics
Document #: 38-03014 Rev. *A
t
t
t
f
Parameter
AWH
AWL
ACNT
ACNT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
IN
IO
EXP
LAD
LAC
OD
ZX
XZ
RSU
RH
LATCH
RD
COMB
IC
ICS
FD
PRE
CLR
PIA
IN
IO
EXP
LAD
LAC
OD
ZX
XZ
RSU
RH
LATCH
RD
7.
8.
Parameter
[8]
[8]
C1 = 5 pF.
Sample tested only for an output change of 500 mV.
[9]
Asynchronous Clock Input HIGH Time
Asynchronous Clock Input LOW Time
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay
Output Buffer Disable Delay
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
Register Delay
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Programmable Interconnect Array Delay Time
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay
Output Buffer Disable Delay
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
Register Delay
Description
[3]
[3]
Description
[7]
[7]
[3]
[3]
[5]
[5]
[5]
Min.
Min.
7C342B-15
7C342B-15
2
7
6
4
11
50
9
Over Operating Range
Max.
Over Operating Range (continued)
Max.
10
12
12
10
10
10
20
3
3
8
8
5
3
5
5
1
1
1
6
0
1
3
3
5
6
5
3
1
Min.
Min.
7C342B–20
7C342B-20
10
14
11
40
1
8
6
CY7C342B
Max.
Max.
25
10
12
13
14
14
12
11
11
Page 7 of 14
4
4
5
3
5
5
1
1
1
8
0
1
3
3
7
6
5
4
2
Unit
33.3
Unit
16
14
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8