CY7C342B-15JC Cypress Semiconductor Corp, CY7C342B-15JC Datasheet - Page 6

• Manufacturer Part Number: CY7C342B-15JC
• Description: IC EPLD 128MACROCELL 15NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C342B-15JC

• Programmable Type: EPLD
• Number Of Macrocells: 128
• Voltage - Input: 5V
• Speed: 15ns
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: MAX®
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 52
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Memory Type: EPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1262

Commercial and Industrial External Synchronous Switching Characteristics
Commercial and Industrial External Synchronous Switching Characteristics
Commercial and Industrial External Asynchronous Switching Characteristics
Document #: 38-03014 Rev. *A
t
t
t
t
t
t
f
t
t
t
Notes:
Parameter
t
t
t
t
t
t
t
f
t
f
Parameter
t
t
t
t
t
t
t
f
t
t
f
ACO1
AS1
AH
AWH
AWL
ACNT
ACNT
ACO1
AS1
AH
3.
4.
5.
6.
PD1
PD2
SU
CO1
H
WH
WL
MAX
CNT
CNT
PD1
PD2
SU
CO1
H
WH
WL
MAX
CNT
ODH
CNT
Parameter
C1 = 35 pF.
The f
This parameter is measured with a 16-bit counter programmed into each LAB
This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t
MAX
values represent the highest frequency for pipeline data.
Asynchronous Clock Input to Output Delay
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time
Asynchronous Clock Input LOW Time
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
Asynchronous Clock Input to Output Delay
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input
Input Hold Time from Asynchronous Clock Input
Dedicated Input to Combinatorial Output Delay
I/O Input to Combinatorial Output Delay
Global Clock Set-Up time
Synchronous Clock Input to Output Delay
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency
Minimum Global Clock Period
Output Data Hold Time After clock
Maximum Internal Global Clock Frequency
Dedicated Input to Combinatorial Output Delay
I/O Input to Combinatorial Output Delay
Global Clock Set-Up time
Synchronous Clock Input to Output Delay
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency
Minimum Global Clock Period
Maximum Internal Global Clock Frequency
Description
Description
Description
[6]
[6]
[4]
[3]
[4]
[5]
[3]
[3]
[3]
[3]
[5]
[3]
[5]
[3]
[3]
Min.
62.5
7C342B-25
15
50
0
8
8
2
Max.
[6]
[5]
25
40
14
20
Min.
83.3
100
7C342B-15
10
Min.
83.3
0
5
5
7C342B-15
5
5
5
5
5
6
Min.
7C342B-30
20
10
10
50
40
0
2
AWH
Max.
15
25
12
Max.
8
and t
15
12
25
Over Operating Range
Max.
30
45
16
25
Over Operating Range
Over Operating Range
AWL
Min.
71.4
66.7
7C342B-20
parameters must be swapped.
13
Min.
66.7
0
7
7
7C342B–20
Min.
7C342B-35
12.5
12.5
33.3
6
6
7
7
6
8
25
40
0
2
CY7C342B
Max.
Max.
20
33
15
Max.
9
20
15
30
35
55
20
30
Page 6 of 14
MHZ
MHz
Unit
MHz
Unit
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns