ATF16V8BQ-10JC Atmel, ATF16V8BQ-10JC Datasheet - Page 7

• Manufacturer Part Number: ATF16V8BQ-10JC
• Description: IC PLD 8CELL QTR PWR 10NS 20PLCC
• Manufacturer: Atmel

Specifications of ATF16V8BQ-10JC

• Programmable Type: EE PLD
• Number Of Macrocells: 8
• Voltage - Input: 5V
• Speed: 10ns
• Mounting Type: Surface Mount
• Package / Case: 20-PLCC
• Family Name: ATF16V8BQ
• Process Technology: CMOS
• # Macrocells: 8
• # I/os (max): 8
• Frequency (max): 83MHz
• Propagation Delay Time: 10ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.6
4.7
5. Security Fuse Usage
0364J–PLD–7/05
Power-up Reset
Preload of Registered Outputs
The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayed
slightly from V
tered output state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
required:
Figure 4-1.
Table 4-2.
The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either
a high or a low. This feature will simplify testing since any state can be forced into the registers
to control test sequencing. A JEDEC file with preload is generated when a source file with vec-
tors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically
by most of the approved programmers after the programming.
A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once
programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains
accessible.
The security fuse should be programmed last, as its effect is immediate.
Parameter
t
V
1. The V
2. After reset occurs, all input and feedback setup times must be met before driving the
3. The clock must remain stable during t
PR
RST
clock pin high, and
CC
CC
rise must be monotonic,
Power-up Reset Waveforms
Power-up Reset Parameters
crossing V
Description
Power-up
Reset Time
Power-up
Reset Voltage
RST
, all registers will be reset to the low state. As a result, the regis-
CC
actually rises in the system, the following conditions are
PR
.
Typ
600
3.8
ATF16V8B/BQ/BQL
1,000
Max
4.5
Units
ns
V
7