MMA8110EGR2 Freescale Semiconductor, MMA8110EGR2 Datasheet - Page 44

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MMA8110EGR2

Manufacturer Part Number
MMA8110EGR2
Description
Board Mount Accelerometers Z-AXIS 100G W/CAP BOND
Manufacturer
Freescale Semiconductor
Series
MMA81r
Datasheet

Specifications of MMA8110EGR2

Sensing Axis
Z
Acceleration
100 g
Sensitivity
4.01 mV/g
Package / Case
SOIC-20 Wide
Axis
Z
Acceleration Range
±100g
Voltage - Supply
6.3 V ~ 30 V
Output Type
Digital
Bandwidth
-
Interface
SPI
Mounting Type
Surface Mount
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
A.4.3 Register Array Write Operation
A write operation is completed through the transfer of a 16-bit value using the SPI as shown in the diagram below. Data present
at the D
Contents of the register at the time the write operation is initiated are presented at the D
edges of the CLK input.
A.4.4 Internal Address Map Overview
OTP data is transferred to internal registers during the first sixteen clock cycles following oscillator startup and negation of internal
reset. When the device operates in test mode, OTP data in the mirror registers may be overwritten. Mirror register writes must
be enabled by setting the SPI_WRITE_ENABLE bit (address $29[5]). This bit may be set by writing the value $0 to address $20.
Internal register read and write operations are described in
MMA81XXEG
44
IN
pin are transferred to the register at the associated address during the 9th through 16th rising edges at the CLK input.
D
IN
D
CLK
/V
OUT
P2
A[5] A[4] A[3] A[2] A[1] A[0] RW
1
Figure A-5. Serial Data Timing, Register Array Write Operation
2
3
4
5
6
Section
7
8
3.
D[7]
D[7]
9
D[6] D[5] D[4] D[3] D[2] D[1] D[0]
D[6 D[5] D[4] D[3] D[2] D[1] D[0]
10
OUT
11
pin during the 8th through 15th falling
12
13
Freescale Semiconductor
14
15
16
Sensors

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