QU80386EXTC25 Intel, QU80386EXTC25 Datasheet - Page 15

• Manufacturer Part Number: QU80386EXTC25
• Description: IC INT PROC 5V 25MHZ 132QFP
• Manufacturer: Intel

Specifications of QU80386EXTC25

• Processor Type: 386EX
• Features: 32-bit, Extended Temp
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 863826

Datasheet
Table 4.
Intel386™ EX Microprocessor Pin Descriptions (Sheet 3 of 6)
INT9:0
LBA#
LOCK#
M/IO#
NA#
NMI
PEREQ
P1.5:0
P1.7:6
P2.7,4:0
P2.6:5
P3.7:0
NOTES:
1. X if clock source is internal; Q if clock source is external
2. Q if JTAG unit is shifting out data, Z if it is not
Symbol
Type
ST
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
Output States
R(WH)
R(WH)
R(WH)
R(WL)
R(WL)
R(WL)
H(1)
R(1)
P(X)
H(Z)
P(X)
H(Z)
R(0)
H(X)
P(X)
H(X)
P(X)
H(X)
P(X)
H(X)
P(X)
H(X)
P(X)
P(1)
I(Q)
I(X)
I(X)
I(X)
I(X)
I(X)
I(X)
I(1)
Interrupt Requests are maskable inputs that cause the CPU to
suspend execution of the current program and then execute an
interrupt acknowledge cycle. They are multiplexed as follows:
INT9 with TMROUT0 and P3.0, INT8 with TMROUT1 and P3.1,
INT7 with TMRGATE1, INT6 with TMRCLK1, INT5 with
TMRGATE0, INT4 with TMRCLK0, and INT3:0 with P3.5:2.
INT9, INT8, and INT3:0 have temporary weak pull-down
resistors.
Local Bus Access is asserted whenever the processor provides
the READY# signal to terminate a bus transaction. This occurs
when an internal peripheral address is accessed or when the
chip-select unit provides the READY# signal.
Bus Lock prevents other bus masters from gaining control of the
system bus.
LOCK# is multiplexed with P1.5.
Memory/IO Indicates whether the current bus cycle is a memory
cycle or an I/O cycle. When M/IO# is HIGH, the bus cycle is a
memory cycle; when M/IO# is LOW, the bus cycle is an I/O cycle.
Next Address requests address pipelining.
Nonmaskable Interrupt Request is a non-maskable input that
causes the CPU to suspend execution of the current program
and execute an interrupt acknowledge cycle.
Processor Extension Request indicates that the math
coprocessor has data to transfer to the processor. PEREQ is
multiplexed with TMRCLK2 and has a temporary weak pull-down
resistor.
Port 1, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD,
P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with
DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#.
Port 1, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD,
P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with
DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#.
Port 2, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0,
P2.5 with RXD0, and P2.4:0 with CS4:0#.
Port 2, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0,
P2.5 with RXD0, and P2.4:0 with CS4:0#.
Port 3, Pins 7:0 are multipurpose bidirectional port pins. They
are multiplexed as follows: P3.7 with COMCLK, P3.6 with
PWRDOWN, P3.5:2 with INT3:0, and P3.1:0 with TMROUT1:0
and INT8:9.
Intel386™ EX Embedded Microprocessor
Name and Function
15