MPC180LMB Freescale Semiconductor, MPC180LMB Datasheet - Page 41

• Manufacturer Part Number: MPC180LMB
• Description: IC SECURITY PROCES 66MHZ 100LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MPC180LMB

• Processor Type: Security Processor
• Speed: 66MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Reset
Field
Addr
R/W
5.1.2 Control Register
Figure 5-2 shows the AFEU Control Register.
Table 5-3 describes the AFEU Control Register fields.
5.1.3 Clear Interrupt Register
The Clear Interrupt Register is a write-only register. Writing to this register will clear the
IRQ signal and the IRQ bit in the status register. The actual data written to this register is
ignored.
5.1.4 Key Length Register
The Key Length Register is a 4-bit write-only register that stores the number of bytes
(minus one) in the key. Writing to this register will signal the AFEU to start permuting the
memory with the key. Therefore, the key must be written before writing to this register.
5.1.5 Key (Low/Lower-middle/Upper-middle/Upper) Register
Each register is 32-bits wide (write-only). Because the key size may be 1 to 16 bytes in
length, the key data is stored in four individually addressable registers. The key low register
holds the lowest significant four bytes of the key. The Key Lower-Middle Register holds the
next lowest four bytes of the key. The Key Upper-Middle Register holds the next highest
four bytes of the key. The Key Upper Register holds the most significant four bytes of the
key.
Bit
0–29 —
30
31
Name
RST
IMSK
0
Reserved, should be cleared.
The AFEU can be reset by asserting the RESET signal or by setting the Software Reset bit in the
0 —
1 software reset
Clearing the interrupt mask bit will allow interrupts on the IRQ pin. It does not affect the IRQ bit in
the status register. This bit is set (interrupts disabled) any time a hardware/software reset is
performed. The user must clear this bit to enable hardware interrupts.
0 enable interrupts
1 disable interrupts
Control Register. The software and hardware resets are functionally equivalent. The software
reset bit will clear itself one cycle after being set.
Figure 5-2. Arc Four Execution Unit Control Register
Table 5-3. AFEU Control Register Field Descriptions
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 5. Arc Four Execution Unit
Go to: www.freescale.com
—
0000_0000_0000_0001
0x400
Description
W
Arc Four Execution Unit Registers
29
RST
30
IMSK
5-3
31