MPC180LMB Freescale Semiconductor, MPC180LMB Datasheet - Page 34

IC SECURITY PROCES 66MHZ 100LQFP

MPC180LMB

Manufacturer Part Number
MPC180LMB
Description
IC SECURITY PROCES 66MHZ 100LQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC180LMB

Processor Type
Security Processor
Speed
66MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

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EBI Controller Operation
writes or reads the address of the buffer.
DREQ1 and DREQ2 (input/output buffer ready) are programmable handshake signals used
for buffer control. An external DMA controller can use this handshake to service the input
or output buffer with data transfers as required. The EBI CSTAT register determines
whether these signals reflect the state of the input buffer or output buffer. By default,
DREQ1 refers to the state of the input buffer and DREQ2 refers to the state of the output
buffer.
In FIFO mode, the input buffer automatically fills and the output buffer automatically
empties. In the input buffer, this is accomplished by assertion of DREQx whenever at least
eight 32-bit words (in MPC8260 mode) of space are available. Similarly, for the output
buffer, DREQx remains asserted as long as at least eight 32-bit words (MPC8260 mode)
are in the output buffer to be read.
3-12
DREQx refers to either DREQ1 or DREQ2. Either can be
programmed to refer to the state of the input or output buffer.
Freescale Semiconductor, Inc.
MPC180LMB Security Processor User’s Manual
For More Information On This Product,
Go to: www.freescale.com
NOTE:

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