MC68020RC25E Freescale Semiconductor, MC68020RC25E Datasheet - Page 177

• Manufacturer Part Number: MC68020RC25E
• Description: IC MICROPROC 32-BIT 25MHZ 114PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC25E

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: Q1165253

The instruction can include as many as five effective address extension words following
the F-line operation word in the cpRESTORE instruction format. These words contain any
additional information required to calculate the effective address specified by bits 5–0 of
the F-line operation word.
All memory addressing modes except the predecrement addressing mode are valid.
Invalid effective address encodings cause the MC68020/EC020 to initiate F-line emulator
exception processing (refer to 7.5.2.2 F-Line Emulator Exceptions).
7.2.3.4.2 Protocol. Figure 7-18 shows the protocol for the coprocessor context restore
instruction. When the main processor executes a cpRESTORE instruction, it first reads
the coprocessor format word from the effective address in the instruction. This format
word contains a format code and a length field. During cpRESTORE operation, the main
processor retains a copy of the length field to determine the number of bytes to be
transferred to the coprocessor during the cpRESTORE operation and writes the format
word to the restore CIR to initiate the coprocessor context restore.
When the coprocessor receives the format word in the restore CIR, it must terminate any
current operations and evaluate the format word. If the format word represents a valid
coprocessor context as determined by the coprocessor design, the coprocessor returns
the format word to the main processor through the restore CIR and prepares to receive
the number of bytes specified in the format word through its operand CIR.
7-24
M1
OPERATION WORD
M2
EFFECTIVE ADDRESS SPECIFIED IN OPERATION WORD
M3
RESTORE CIR
M4
M5
CODE TO CONTROL CIR AND INITIATE FORMAT ERROR
EXCEPTION PROCESSING (SEE NOTE 1)
M6
NUMBER OF BYTES SPECIFIED BY FORMAT WORD TO
OPERAND CIR (SEE NOTE 2)
M7
NOTES: 1. See 7.6.1.5 Format Error.
IF (FORMAT = INVALID FORMAT) WRITE $0001 ABORT
IF (FORMAT = EMPTY/RESET) GO TO M7; ELSE, TRANSFER
RECOGNIZE COPROCESSOR INSTRUCTION F-LINE
READ COPROCESSOR FORMAT CODE FROM
WRITE COPROCESSOR FORMAT WORD TO
READ RESTORE CIR
PROCEED WITH EXECUTION OF NEXT INSTRUCTION
2. The MC68020/EC020 uses the length field in the format word read during M2 to determine the number of
bytes to read from memory and write to the operand CIR.
Figure 7-18. Coprocessor Context Restore Instruction Protocol
MAIN PROCESSOR
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FORMAT WORD
C1
C2
IN THE RESTORE CIR
C3
INDICATED IN FORMAT WORD THROUGH OPERAND CIR
TERMINATE CURRENT OPERATIONS AND EVALUATE
IF (INVALID FORMAT) PLACE INVALID FORMAT CODE
IF (VALID FORMAT) RECEIVE NUMBER OF BYTES
COPROCESSOR
MOTOROLA