MC68020RC16E Freescale Semiconductor, MC68020RC16E Datasheet - Page 49
MC68020RC16E
Manufacturer Part Number
MC68020RC16E
Description
IC MPU 32BIT 16MHZ 114-PGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68020EH16E.pdf
(306 pages)
Specifications of MC68020RC16E
Processor Type
M680x0 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
114-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16.67MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
114
Package Type
CPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC68020RC16E
Manufacturer:
MOT
Quantity:
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Company:
Part Number:
MC68020RC16E
Manufacturer:
MOT
Quantity:
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Part Number:
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Manufacturer:
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input is high or low. Figure 5-1 shows the relationship between the clock signal, a typical
input, and its associated internal signal.
Furthermore, for all inputs, the processor latches the level of the input during a sample
window around the falling edge of the clock signal. This window is illustrated in Figure 5-2.
To ensure that an input signal is recognized on a specific falling edge of the clock, that
input must be stable during the sample window. If an input transitions during the window,
the level recognized by the processor is not predictable; however, the processor always
resolves the latched level to either a logic high or logic low before using it. In addition to
meeting input setup and hold times for deterministic operation, all input signals must obey
the protocols described in this section.
5.1.1 Bus Control Signals
The MC68020/EC020 initiates a bus cycle by driving the A1–A0, SIZ1, SIZ0, FC2–FC0,
and R/W outputs. However, if the MC68020/EC020 finds the required instruction in the on-
chip cache, the processor aborts the cycle before asserting the AS.The assertion of AS
ensures that the cycle has not been aborted by these internal conditions.
5-2
Figure 5-1. Relationship between External and Internal Signals
EXT
CLK
EXT
INT
CLK
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 5-2. Input Sample Window
M68020 USER’S MANUAL
Go to: www.freescale.com
t su
WINDOW
SAMPLE
SYNC DELAY
t h
MOTOROLA
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