MC68306FC16B Freescale Semiconductor, MC68306FC16B Datasheet - Page 41

• Manufacturer Part Number: MC68306FC16B
• Description: IC MPU INTEGRATED 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68306FC16B

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The descriptions of the read-modify-write cycle states are as follows:
STATE 0
STATE 1
STATE 2
STATE 3
STATE 4
STATE 5
STATE 6
STATE 7
STATES
8–11
MOTOROLA
UDS OR LDS
D15–D8 OR
D7–D0
FC2–FC0
A31–A1
DTACK
CLK
R/W
AS
FC2–FC0, a valid address on the address bus, and drives R/W high to
identify a read cycle.
During S4, the processor waits for a cycle termination signal (DTACK or
The read cycle starts in S0. The processor places valid function codes on
During S1, no bus signals are altered.
On the rising edge of S2, the processor asserts AS and UDS /LDS.
During S3, no bus signals are altered.
BERR ). If neither termination signal is asserted before the falling
edge at the end of S4, the processor inserts wait states (full clock cycles)
until either DTACK or BERR is asserted.
Case R1: DTACK only.
During S5, no bus signals are altered.
During S6, data from the device are driven onto the data bus.
On the falling edge of the clock entering S7, the processor accepts data from
the device and negates UDS /LDS . The device negates DTACK at this
time.
The bus signals are unaltered during S8–S11, during which the arithmetic
logic unit makes appropriate modifications to the data.
Figure 3-9. Read-Modify-Write Cycle Timing Diagram
S0 S1 S2 S3 S4 S5 S6
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S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19
INDIVISIBLE CYCLE
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