TG80960JT100 Intel, TG80960JT100 Datasheet - Page 80

• Manufacturer Part Number: TG80960JT100
• Description: IC MPU I960JT 3V 100MHZ 132-QFP
• Manufacturer: Intel

Specifications of TG80960JT100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: JT suffix, 32-Bit, 16k Cache, Extended Temp
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 132-QFP
• Other names: 824389

80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
7.2
80
Figure 52. Bus States with Arbitration
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and
HIGHZ pins.
Table 42
contain ‘CTL’ select the direction of bidirectional pins or HIGHZ output pins. When a 1 is loaded
into the control cell, the associated pin(s) are HIGHZ or selected as input.
ONCE & RESET
Ti — IDLE STATE
Ta — ADDRESS STATE
Tw / Td — WAIT/DATA STATE
Tr — RECOVERY STATE
Th — HOLD STATE
To — ONCE STATE
DEASSERTION
AND (NO HOLD
NO REQUEST
OR LOCKED)
shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that
To
REQUEST PENDING
AND (NO HOLD OR
RESET
LOCKED)
Ti
Ta
PENDING AND
NOT LOCKED
REQUEST
NO HOLD
HOLD AND
AND NO HOLD
NO REQUEST
HOLD OR LOCKED)
PENDING AND (NO
RECOVERED AND
REQUEST PENDING — NEW TRANSACTION
NOT RECOVERED — RDYRCV# ASSERTED
REQUEST
NO REQUEST — NO NEW TRANSACTION
NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS
RECOVERED — RDYRCV# NOT ASSERTED
NOT READY — RDYRCV# NOT ASSERTED
NO BURST — BLAST# ASSERTED
NO HOLD — HOLD REQUEST NOT ASSERTED
LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
READY — RDYRCV# ASSERTED
BURST — BLAST# NOT ASSERTED
RESET — RESET# ASSERTED
ONCE — ONCE# ASSERTED
HOLD — HOLD REQUEST ASSERTED
Tw/Td
Th
HOLD
NO REQUEST AND
RECOVERED AND
(READY AND BURST)
(NO HOLD OR
OR NOT READY
LOCKED)
READY AND NO BURST
RECOVERED AND
HOLD AND NOT
LOCKED
Tr
RECOVERED
NOT
Datasheet