TG80960JT100 Intel, TG80960JT100 Datasheet - Page 79

• Manufacturer Part Number: TG80960JT100
• Description: IC MPU I960JT 3V 100MHZ 132-QFP
• Manufacturer: Intel

Specifications of TG80960JT100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: JT suffix, 32-Bit, 16k Cache, Extended Temp
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 132-QFP
• Other names: 824389

80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
7.1
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.
Figure 52
shows the five bus states.
The bus occupies the idle (Ti) state when no address/data transactions are in progress and when
RESET# is asserted. When the processor needs to initiate a bus access, it enters the Ta state to
transmit the address.
Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV# input signal indicates completion of each transfer. When data is
not ready, the processor may wait as long as necessary for the memory or I/O device to respond.
After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case
of a burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next
data word. The processor asserts the BLAST# signal during the last Tw/Td states of an access.
Once all data words transfer in a burst access (up to four), the bus enters the Tr state to allow
devices on the bus to recover.
The processor remains in the Tr state until RDYRCV# is deasserted. When the recovery state
completes, the bus enters the Ti state when no new accesses are required. When an access is
pending, the bus enters the Ta state to transmit the new address.
Datasheet
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