A80960KB25 Intel, A80960KB25 Datasheet - Page 4

• Manufacturer Part Number: A80960KB25
• Description: IC MPU I960KB 25MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80960KB25

• Processor Type: i960
• Features: KB suffix, 32-Bit, 512 Byte Cache
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803535

Contents
FIGURES
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80960KA Programming Environment ........................................................................................ 1
Instruction Formats .................................................................................................................... 4
Multiple Register Sets Are Stored On-Chip ............................................................................... 6
Connection Recommendations for Low Current Drive Network .............................................. 11
Connection Recommendations for High Current Drive Network .............................................. 11
Typical Supply Current vs. Case Temperature ......................................................................... 12
Typical Current vs. Frequency (Room Temp) .......................................................................... 12
Typical Current vs. Frequency (Hot Temp) .............................................................................. 13
Worst-Case Voltage vs. Output Current on Open-Drain Pins .................................................. 13
Capacitive Derating Curve ....................................................................................................... 13
Test Load Circuit for Three-State Output Pins ......................................................................... 14
Test Load Circuit for Open-Drain Output Pins .......................................................................... 14
Drive Levels and Timing Relationships for 80960KA Signals .................................................. 16
Processor Clock Pulse (CLK2) ........................................................................................ ........ 20
RESET Signal Timing ................................................................................................. ............. 20
132-Lead Pin-Grid Array (PGA) Package ............................................................................... . 21
80960KA PGA Pinout—View from Bottom (Pins Facing Up) ................................................... 22
80960KA PGA Pinout—View from Top (Pins Facing Down) .................................................... 23
80960KA 132-Lead Plastic Quad Flat-Pack (PQFP) Package ................................................ 23
PQFP Pinout - View From Top ................................................................................................. 24
HOLD Timing ........................................................................................................................... 30
16 MHz Maximum Allowable Ambient Temperature ................................................................ 31
20 MHz Maximum Allowable Ambient Temperature ................................................................ 31
25 MHz Maximum Allowable Ambient Temperature ................................................................ 32
Maximum Allowable Ambient Temperature
for the Extended Temperature 80960KA at 20 MHz in PGA Package ...................................... 32
Burst Read and Write Transaction Without Wait States ........................................................... 34
Burst Write Transaction with 2, 1, 1, 1 Wait States .................................................................. 35
Accesses Generated by Quad Word Read Bus Request,
Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States) .............................. 36
Interrupt Acknowledge Transaction ......................................................................................... 37