A80960KB25 Intel, A80960KB25 Datasheet - Page 14

• Manufacturer Part Number: A80960KB25
• Description: IC MPU I960KB 25MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80960KB25

• Processor Type: i960
• Features: KB suffix, 32-Bit, 512 Byte Cache
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803535

80960KB
8
CLK2
LAD31:0
ALE
ADS
W/R
DT/R
DEN
READY
LOCK
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
NAME
ERRATA - 6/13/97
DEN pin description omitted.
TYPE
O.D.
O.D.
O.D.
O.D.
O.D.
T.S.
T.S.
I/O
I/O
O
O
O
O
O
I
I
Table 4. 80960KB Pin Description: L-Bus Signals (Sheet 1 of 2)
SYSTEM CLOCK provides the fundamental timing for 80960KB systems. It is
divided by two inside the 80960KB and four 80-bit registers (FP0 through FP3) to
generate the internal processor clock.
LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to
and from memory. During an address (T
address (bits 0-1 indicate SIZE; see below). During a data (T
contain read or write data. These pins float to a high impedance state when not
active.
Bits 0-1 comprise SIZE during a T
words.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a T
is active LOW and floats to a high impedance state during a hold cycle (T
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T
state and deasserted during the following T
asserted again every T
WRITE/READ specifies, during a T
read. It is latched on-chip and remains valid during T
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from
the L-Bus. It is low during T
edgment; it is high during T
when DEN is asserted.
DATA ENABLE (active low) enables data transceivers. The processor asserts
DEN# during all Td and Tw states. The DEN# line is an open drain-output of the
80960KB-processor.
READY indicates that data on LAD lines can be sampled or removed. If READY
is not asserted during a T
inserting a wait state (T
BUS LOCK prevents bus masters from gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK.
At the start of a RMW operation, the processor examines the LOCK pin. If the pin
is already asserted, the processor waits until it is not asserted. If the pin is not
asserted, the processor asserts LOCK during the T
The processor deasserts LOCK in the T
time LOCK is asserted, a bus agent can perform a normal read or write but not a
RMW operation.
The processor also asserts LOCK during interrupt-acknowledge transactions.
Do not leave LOCK unconnected. It must be pulled high for the processor to
function properly.
LAD1
0
0
1
1
LAD0
0
1
0
1
a
cycle and deasserted before the beginning of the T
d
w
) and ADS is not asserted in the next cycle.
state where READY was asserted in the previous cycle.
d
a
cycle, the T
a
and T
and T
1 Word
2 Words
3 Words
4 Words
DESCRIPTION
a
d
d
a
cycle. SIZE specifies burst transfer size in
cycles for a write. DT/R never changes state
cycles for a read or interrupt acknowl-
cycle, whether the operation is a write or
d
a
a
cycle is extended to the next cycle by
) cycle, bits 2-31 contain a physical word
cycle of the write transaction. During the
d
state. For a burst transaction, ADS is
a
cycle of the read transaction.
d
cycles.
d
) cycle, bits 0-31
d
state. It
h
).
a