PCX745BVZFU350LE Atmel, PCX745BVZFU350LE Datasheet - Page 26

• Manufacturer Part Number: PCX745BVZFU350LE
• Description: IC MPU 32BIT 350MHZ 255PBGA
• Manufacturer: Atmel

Specifications of PCX745BVZFU350LE

• Processor Type: PowerPC 32-Bit RISC
• Speed: 350MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 255-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 8-3.
Notes:
26
Parameter
Mode select input setup to HRESET
HRESET to mode select input hold
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
2. THe symbology used for timing specifications herein follows the pattern of t
3. The setup and hold time is with respect to the rising edge of HRESET (see
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of
5. t
6. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0
7. Guaranteed by design and characterization.
8. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during operation
PC755/745
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-
nal in question. All output timings assume a purely resistive 50Ω load (See
measured at the pin; time
t
the SYSCLK reference (K) going to the high (H) state or input setup time. And t
going highs) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal
(I) went invalid (X) with respect to the rising clock edge (KH)
output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). For additional explana-
tion of AC timing specifications in Freescale PowerPC microprocessors, see the application note “Understanding AC Timing
Specifications for PowerPC Microprocessors.”
255 bus clocks after the PLL re
by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
will cause the bus mode voltage selection to change. Changing the logic states of the PLL_CFG pins during operation will
cause the PLL division ratio selection to change. Both of these conditions are considered outside the specification and are
not supported. Once HRESET is negated the states of the bus mode selection pins must remain stable.
(reference)(state)(signal)(state)
SYSCLK
Processor Bus Mode Selection AC Timing Specifications
At
OV
V
DD
is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
DD
= 2.0V 100 mV
= A
V
DD
Figure 8-2
Figure 8-2.
Figure 8-3
Figure 8-3.
= 2.0V 100 mV; -55 ≤ T
Mode Signals
for outputs. For example, t
(3)(4)(6)(7)(8)
HRESET
(3)(4)(5)(6)(7)
-
of
-
provides the mode select input timing diagram for the PC755.
provides the AC test load for the PC755.
flight delays must be added for trace lengths, vias, and connectors in the system.
-
lock time during the power
OUTPUT
Mode Input Timing Diagram
AC Test Load
Symbols
J
≤ +125
t
t
MVRH
MXRH
IVKH
VM = Midpoint Voltage (OV DD /2)
°
symbolizes the time input signals (I) reach the valid state (V) relative to
(2)
C, OV
t MVRH
-
3]
Z 0 = 50Ω
-
on reset sequence.
-
DD
note the position of the reference and its state for inputs
= 3.3V 165 mV and OV
(1)
Min
8
0
VM
All Speed Grades
Figure
(signal)(state)(reference)(state)
Figure
KHOV
t MXRH
8-2). Input and output timings are
8-2).
symbolizes the time from SYSCLK(K)
R
L
= 50Ω
DD
Max
–
–
= 1.8V
for inputs and
OV DD /2
±
100 mV and
2138G–HIREL–05/06
t
SYSCLk
Unit
ns
–
and