XS1-L01A-TQ128-C4 XMOS, XS1-L01A-TQ128-C4 Datasheet - Page 2

• Manufacturer Part Number: XS1-L01A-TQ128-C4
• Description: IC MPU 32BIT SINGLE CORE 128TQFP
• Manufacturer: XMOS

Specifications of XS1-L01A-TQ128-C4

• Processor Type: XCore 32-Bit
• Speed: 400MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP Exposed Pad, 128-eTQFP, 128-HTQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1002; XS1-L01-TQ128-C4

XS1-L1 128TQFP Datasheet (2.2)
1 Description
XS1-L1 Description
A high performance switch supports low latency and de-
XS1-L1 128TQFP Package Features
XCore Resources
The XS1-L1 is a member of the XS1-L family of XMOS de-
vices. The XS1-L family blends a powerful programmable
fabric based on multi-threaded processors with a high-
level programming language design flow. XMOS chips are
general-purpose programmable devices that can be used
in a wide range of applications and systems.
The XS1-L1 device is based on the XMOS XCore™. Each
XCore contains a 32-bit processor, SRAM memory, I/O
ports for communicating with external components and
channels for communicating with other devices.
One Time Programmable (OTP) memory is provided for ap-
plication boot code and security keys, with a secure mode
that disables debug and prevents read-back of memory
contents.
terministic communication between threads in different
XCores.
The XMOS architecture is unique in its direct support for
concurrent processing (multi-threading), event handling,
communication and timed I/O operations.
One XCore providing 400/500MIPS and eight concurrent, deterministic real-time tasks
64 user I/O pins, dynamically configurable as input, output or bi-directional
Threads
Channel Ends
Timers
Clock Blocks
XMOS Links
Thread Synchronisers
Hardware Locks
SRAM
OTP Memory
8
32
10
6 (includes the reference clock)
4 (5bit or 2bit)
7
4
64KBytes
8KBytes
Links
1 x 32bit
2 x 16bit
16 x 1bit
8KBytes
Output
4 x 8bit
6 x 4bit
Input/
I/O
Ports
JTAG
OTP
TAP
7 Synchronisers
JTAG
10 Timers
Ctrl
8 Threads per XCore
Constant Pointer
XS1-L1
Stack Pointer
Link Register
Processor
Data Pointer
XCore
Per Thread
Reg 0
Reg 1
Reg 2
Reg 3
Reg 4
Reg 5
Reg 6
Reg 7
Reg 8
Reg 9
Reg 10
Reg 11
XCore
Switch
JTAG Debug
64KBytes SRAM
6 Clock Blocks
PLL
4 Locks
Links
Channel
I/O
Ends
(32)
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