XS1-L01A-TQ128-C4 XMOS, XS1-L01A-TQ128-C4 Datasheet
XS1-L01A-TQ128-C4
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XS1-L01-TQ128-C4
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XS1-L01A-TQ128-C4 Summary of contents
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... XS1-L1 128TQFP Datasheet Publication Date: 2010/12/02 Copyright © 2010 XMOS Limited, All Rights Reserved. Version 2.2 ...
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... XS1-L1 128TQFP Datasheet (2.2) 1 Description XS1-L1 Description The XS1- member of the XS1-L family of XMOS de- vices. The XS1-L family blends a powerful programmable fabric based on multi-threaded processors with a high- level programming language design flow. XMOS chips are general-purpose programmable devices that can be used in a wide range of applications and systems. The XS1-L1 device is based on the XMOS XCore™ ...
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... 2.1 XCore Signals The XS1-L1 128 TQFP device provides 64 XCore signals that can be used for generic I/O ports or for XMOS Links. 2.1.1 XCore signals as I/O ports The following table shows the I/O ports available on the XCore processor. Each port is bidirectional. See Section TQFP device ...
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... XS1-L1 128TQFP Datasheet (2.2) 2.1.3 Precedence Ports and XMOS Links are connected to pins on the XS1-L1 by the program running on the device. The ports and links are multiplexed and follow a defined precedence if they overlap on the same core XMOS Link is enabled, the link has access to the pins; the pins of the underlying ports are disabled ...
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... XS1-L1 128TQFP Datasheet (2.2) 2.2 Port Pin Table Package XMOS Links Pin Name Pin ID 5bit X0D0 37 X0D1 36 X0LA4out X0D2 34 X0LA3out X0D3 30 X0LA2out X0D4 28 X0LA1out X0D5 27 X0LA0out X0D6 16 X0LA0in X0D7 14 X0LA1in X0D8 10 X0LA2in X0D9 7 X0LA3in X0D10 5 X0LA4in X0D11 2 X0D12 128 X0D13 126 ...
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... XS1-L1 128TQFP Datasheet (2.2) 2.3 System Service Pins Pin ID Signal 25 CLK 42 DEBUG 51 MODE0 52 MODE1 53 MODE2 55 MODE3 45 OTP_VDDIO 46 OTP_VPP 2.4 Core Power and Ground Pins Pin ID Signal 12 VDD 29 VDD 49 VDD 59 VDD 68 VDD 74 VDD 77 VDD 83 VDD 101 VDD 108 VDD 123 VDD Pin ID ...
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... XS1-L1 128TQFP Datasheet (2.2) 2.5 XCore I/O Power Pins Pin ID Signal 1 VDDIO 15 VDDIO 26 VDDIO 32 VDDIO 44 VDDIO 50 VDDIO 64 VDDIO 2.6 PCU Signal Pins Pin ID Signal 19 PCU_VDD 22 PCU_VDDIO 24 PCU_CLK 2.7 XMOS Link Pins See Section 2.2 Port Pin Table Pin ID Signal 73 VDDIO 79 VDDIO ...
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... XS1-L1 128TQFP Datasheet (2.2) 3 System Services System Services are required to support correct device behavior. These signals control clocking, reset and boot behavior of the device. 3.1 Clock control signals These signals control the on-chip PLL of the XS1-L1 Signal Pin ID PLL_AVDD 48 PLL_AGND 47 CLK ...
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... Following a reset the PLL re-establishes lock after which the device boots up according to the boot mode (see MODE). 3.3 SPI Interface When booting the XS1-L1 device from a SPI interface, the SPI device must be connected to the XS1-L1 as follows: PLL reference clk Boot Frequency 4 ...
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... X0D11 2 3.4 Power Control Unit The XS1-L1 power control unit (PCU) provides control signals to isolate the core voltage of the device and reapply it under a controlled condition known as sleep mode. The device recovers into functional mode under the control of an external PCU_WAKE signal or an internal timer. ...
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... OTP_VPP OTP Programming Voltage (can be used for faster program times otherwise internal charge pump is used). Nom 6.5V if used. 3.6 JTAG Operation The XS1-L1 device contains a standard 5 pin JTAG interface, which allows the following functionality: Boundary scan testing for verifying printed circuit board connectivity. ...
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... XS1-L1 128TQFP Datasheet (2.2) The boundary scan TAP is a standard 1149.1 compliant TAP and can be used for boundary scan of the I/O pins of the device. The chip TAP allows access into the XCore, Switch and OTP for such actions as loading code and debugging. Both TAPs have a bypass register, an instruction register length data register length of 32 and a TDO register ...
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... XS1-L1 128TQFP Datasheet (2.2) Bit31 Version 3.6.2 Usercode register The JTAG usercode register can be read by using the USERCODE instruction. Its contents are specified as follows: Bit31 OTP User The OTP User ID is read from the OTP and can be programmed as a means of identifying versions of OTP programmed devices ...
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... XS1-L1 128TQFP Datasheet (2. and Switching Characteristics 4.1 Operating Conditions Symbol Parameter VDD(IO) I/O DC supply voltage VDD(CORE) Core DC supply voltage AVDD(PLL) PLL analogue supply Cl XCore I/O load capacitance Operating range (Commercial) Ta Operating range (Industrial) Tj Junction temperature Tstg Storage temperature 4.2 DC Characteristics Symbol Parameter ...
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... XS1-L1 128TQFP Datasheet (2.2) 4.3 ESD Stress Voltage ESD Model ESD Stress Voltage HBM 2 200 V 4.4 Reset Timing Parameters Reset pulse width Initialisation time Notes: 1. This parameter shows the time taken to start booting after RST_N has gone high. 4.5 Power Supply Power is applied to the device through the VDDIO and VDD pins. Several pins of each type are provided to minimize the eff ...
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... For a more detailed analysis see 4.6 Clock XS1-L devices use an input clock frequency, supplied by the user on the CLK pin, to drive the PLL and obtain the system clock. The nominal frequency of the clock for all XS1 family components is 20MHz but other clock frequencies can be used ...
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... Assumes typical core and I/O voltages, with nominal activity. 4.7 Memory 4.7.1 Internal static memory The XS1-L1 has a total of 64KBytes of fast internal static memory for high rates of data throughput. Each internal memory access consumes one core clock cycle. There is no dedicated external memory interface, although memory can be expanded through appropriate use of the ports ...
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... ClkBlk The Input Valid window parameter relates to the capability of the XS1-L1 family devices to capture data input to the chip with respect to an external clock source. This parameter can be calculated as the sum of the input setup time and input hold time with regard to the external clock as measured at the L1 device pins. The output invalid window specifi ...
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... XS1-L1 128TQFP Datasheet (2.2) not important in a multi-clock system, providing each meets the required stability criteria. 4.10 JTAG Timing All JTAG operations are synchronous to TCK apart from the global asynchronous reset TRST_N. Parameters TCK frequency (debug) TCK frequency (boundary scan) T SETUP ...
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... XS1-L1 128TQFP Datasheet (2.2) 5 Package Details 5.1 Package Pin Layout The following diagram shows the pin names and locations for the 128 TQFP package. X0D56 33 X0D2 34 X0D57 35 X0D1 36 X0D0 37 X0D58 38 GND 39 GND 40 GND 41 DEBUG 42 GND 43 VDDIO 44 OTP_VDDIO 45 OTP_VPP 46 PLL_AGND 47 PLL_AVDD 48 VDD 49 ...
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... XS1-L1 128TQFP Datasheet (2.2) 5.2 Package Mechanical Details 21/26 ...
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... XS1-L1 128TQFP Datasheet (2.2) 5.3 Package Marking Details USMMYYL1 C5 LLLLLL.LL Manufacture Date Code USMMYYL1 USMMYYL1 C5 USMMYYL1 I4 USMMYYL1 I5 Manufacturing Date Code Qualification/Speed(Optional) Lot Code Part Number XS1-L01A-TQ128-C4 XS1-L01A-TQ128-C5 XS1-L01A-TQ128-I4 XS1-L01A-TQ128-I5 22/26 ...
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... Package Type Pin Count Temp Grade (C commercial 0-70C) Speed Grade (4 normal speed) 6.1 Orderable part numbers Part Number Speed XS1-L01A-TQ128-C4 400MIPS 128 pin TQFP 0.4mm pitch XS1-L01A-TQ128-C5 500MIPS 128 pin TQFP 0.4mm pitch XS1-L01A-TQ128-I4 400MIPS 128 pin TQFP 0.4mm pitch XS1-L01A-TQ128-I5 500MIPS 128 pin TQFP 0 ...
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... Device Configuration Example schematic diagrams detailing minimal system configurations may be found at: http://xmos.com/support/silicon 8 Addendum 8.1 USB ULPI Mode When using the XS1-L1 with ULPI, the ULPI signals must only be connected to the following pins: Pin Name Pin ID X0D12 128 X0D13 ...
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... XS1-L System Specification XMOS Tools User Guide XS1 Assembly Language Manual XMOS XS1 32-Bit Application Binary Interface XS1-L Clock Frequency Control Application Note XS1 Port I/O Timing Application Note XS1-L Link Performance and Design Guidelines Estimating Power Consumption For XS1-L Devices ...
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... XS1-L1 128TQFP Datasheet (2.2) 11 Errata To guarantee a logic low is seen on the following pins, the driving circuit should present an impedance of less than 100 ohms to ground. Pin 55, 53, 52 Usually this is not a problem for CMOS drivers driving single inputs, however, if one or more of these inputs are placed in parallel, additional logic buffers may be required to guarantee correct operation ...